Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.59	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	18	2	16	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	18	2	16	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	275	1			T141	4		T142	7		T178	7
all_values[1]	275	1			T141	4		T142	7		T178	7
all_values[2]	275	1			T141	4		T142	7		T178	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

448

1

T141

8

T142

14

T178

10

auto[1]

377

1

T141

4

T142

7

T178

11

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

369

1

T141

5

T142

6

T178

12

auto[1]

456

1

T141

7

T142

15

T178

9

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

494

1

T141

6

T142

12

T178

14

auto[1]

331

1

T141

6

T142

9

T178

7

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	18	2	16	88.89	2
Automatically Generated Cross Bins	18	2	16	88.89	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

63

1

T141

2

T178

3

T173

1

all_values[0]

auto[0]

auto[0]

auto[1]

27

1

T142

2

T179

1

T180

1

all_values[0]

auto[0]

auto[1]

auto[0]

43

1

T142

1

T178

2

T174

1

all_values[0]

auto[0]

auto[1]

auto[1]

40

1

T142

2

T178

1

T181

4

all_values[0]

auto[1]

auto[0]

auto[1]

59

1

T141

2

T142

1

T178

1

all_values[0]

auto[1]

auto[1]

auto[1]

43

1

T142

1

T181

2

T173

1

all_values[1]

auto[0]

auto[0]

auto[0]

83

1

T141

1

T142

2

T178

2

all_values[1]

auto[0]

auto[1]

auto[0]

78

1

T141

1

T142

1

T178

3

all_values[1]

auto[1]

auto[0]

auto[1]

65

1

T141

1

T142

3

T178

2

all_values[1]

auto[1]

auto[1]

auto[1]

49

1

T141

1

T142

1

T181

1

all_values[2]

auto[0]

auto[0]

auto[0]

59

1

T141

1

T142

1

T181

1

all_values[2]

auto[0]

auto[0]

auto[1]

33

1

T142

2

T181

1

T182

1

all_values[2]

auto[0]

auto[1]

auto[0]

43

1

T142

1

T178

2

T181

1

all_values[2]

auto[0]

auto[1]

auto[1]

25

1

T141

1

T178

1

T181

2

all_values[2]

auto[1]

auto[0]

auto[1]

59

1

T141

1

T142

3

T178

2

all_values[2]

auto[1]

auto[1]

auto[1]

56

1

T141

1

T178

2

T183

2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal