Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100447697	1			T1	3150		T2	116805		T15	317
all_values[1]	100447697	1			T1	3150		T2	116805		T15	317
all_values[2]	100447697	1			T1	3150		T2	116805		T15	317

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

618010

1

T1

40

T2

2592

T15

35

auto[1]

300725081

1

T1

9410

T2

347823

T15

916

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299809068

1

T1

8571

T2

349302

T15

909

auto[1]

1534023

1

T1

879

T2

1113

T15

42

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	206779	1			T2	2102		T15	10		T6	2
all_values[0]	auto[0]	auto[1]	2173	1			T2	6		T15	4		T7	2
all_values[0]	auto[1]	auto[0]	99729577	1			T1	2857		T2	114332		T15	293
all_values[0]	auto[1]	auto[1]	509168	1			T1	293		T2	365		T15	10
all_values[1]	auto[0]	auto[0]	167472	1			T1	31		T2	200		T15	10
all_values[1]	auto[0]	auto[1]	1577	1			T1	3		T2	2		T15	4
all_values[1]	auto[1]	auto[0]	99768884	1			T1	2826		T2	116234		T15	293
all_values[1]	auto[1]	auto[1]	509764	1			T1	290		T2	369		T15	10
all_values[2]	auto[0]	auto[0]	238299	1			T1	5		T2	281		T15	5
all_values[2]	auto[0]	auto[1]	1710	1			T1	1		T2	1		T15	2
all_values[2]	auto[1]	auto[0]	99698057	1			T1	2852		T2	116153		T15	298
all_values[2]	auto[1]	auto[1]	509631	1			T1	292		T2	370		T15	12