Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
351022 |
1 |
|
|
T1 |
2 |
|
T2 |
172 |
|
T15 |
18 |
auto[1] |
343664 |
1 |
|
|
T1 |
398 |
|
T2 |
390 |
|
T6 |
18 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173778 |
1 |
|
|
T1 |
116 |
|
T2 |
133 |
|
T15 |
2 |
lower_val |
171596 |
1 |
|
|
T1 |
108 |
|
T2 |
130 |
|
T15 |
5 |
zero_val |
1887 |
1 |
|
|
T1 |
1 |
|
T2 |
8 |
|
T15 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
260146 |
1 |
|
|
T1 |
106 |
|
T2 |
202 |
|
T15 |
10 |
lower_val |
262446 |
1 |
|
|
T1 |
100 |
|
T2 |
176 |
|
T15 |
8 |
zero_val |
172094 |
1 |
|
|
T1 |
194 |
|
T2 |
184 |
|
T6 |
10 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
43798 |
1 |
|
|
T2 |
27 |
|
T30 |
520 |
|
T32 |
567 |
higher_val |
higher_val |
auto[1] |
21204 |
1 |
|
|
T1 |
26 |
|
T2 |
25 |
|
T6 |
3 |
higher_val |
lower_val |
auto[0] |
44171 |
1 |
|
|
T2 |
15 |
|
T15 |
2 |
|
T30 |
554 |
higher_val |
lower_val |
auto[1] |
21648 |
1 |
|
|
T1 |
28 |
|
T2 |
25 |
|
T31 |
4 |
higher_val |
zero_val |
auto[0] |
81 |
1 |
|
|
T6 |
1 |
|
T23 |
1 |
|
T193 |
1 |
higher_val |
zero_val |
auto[1] |
42876 |
1 |
|
|
T1 |
62 |
|
T2 |
41 |
|
T6 |
4 |
lower_val |
higher_val |
auto[0] |
43176 |
1 |
|
|
T2 |
18 |
|
T15 |
2 |
|
T30 |
551 |
lower_val |
higher_val |
auto[1] |
21056 |
1 |
|
|
T1 |
28 |
|
T2 |
23 |
|
T31 |
1 |
lower_val |
lower_val |
auto[0] |
43507 |
1 |
|
|
T2 |
23 |
|
T15 |
3 |
|
T30 |
613 |
lower_val |
lower_val |
auto[1] |
21348 |
1 |
|
|
T1 |
34 |
|
T2 |
26 |
|
T31 |
4 |
lower_val |
zero_val |
auto[0] |
92 |
1 |
|
|
T2 |
1 |
|
T35 |
1 |
|
T73 |
1 |
lower_val |
zero_val |
auto[1] |
42417 |
1 |
|
|
T1 |
46 |
|
T2 |
39 |
|
T31 |
9 |
zero_val |
higher_val |
auto[0] |
569 |
1 |
|
|
T15 |
1 |
|
T30 |
3 |
|
T32 |
2 |
zero_val |
higher_val |
auto[1] |
135 |
1 |
|
|
T2 |
1 |
|
T74 |
1 |
|
T14 |
1 |
zero_val |
lower_val |
auto[0] |
584 |
1 |
|
|
T2 |
1 |
|
T30 |
2 |
|
T31 |
1 |
zero_val |
lower_val |
auto[1] |
137 |
1 |
|
|
T14 |
1 |
|
T194 |
1 |
|
T46 |
1 |
zero_val |
zero_val |
auto[0] |
259 |
1 |
|
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
zero_val |
zero_val |
auto[1] |
203 |
1 |
|
|
T2 |
6 |
|
T74 |
1 |
|
T194 |
1 |