Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100447697	1			T1	3150		T2	116805		T15	317
all_pins[1]	100447697	1			T1	3150		T2	116805		T15	317
all_pins[2]	100447697	1			T1	3150		T2	116805		T15	317

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	300524711	1			T1	9152		T2	344437		T15	941
values[0x1]	818380	1			T1	298		T2	5978		T15	10
transitions[0x0=>0x1]	816376	1			T1	298		T2	5940		T15	10
transitions[0x1=>0x0]	816398	1			T1	298		T2	5941		T15	10

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99938529	1			T1	2857		T2	116440		T15	307
all_pins[0]	values[0x1]	509168	1			T1	293		T2	365		T15	10
all_pins[0]	transitions[0x0=>0x1]	509157	1			T1	293		T2	365		T15	10
all_pins[0]	transitions[0x1=>0x0]	6297	1			T1	5		T2	3		T19	62
all_pins[1]	values[0x0]	100441389	1			T1	3145		T2	116802		T15	317
all_pins[1]	values[0x1]	6308	1			T1	5		T2	3		T19	62
all_pins[1]	transitions[0x0=>0x1]	6103	1			T1	5		T2	3		T19	62
all_pins[1]	transitions[0x1=>0x0]	302699	1			T2	5610		T7	498		T19	592
all_pins[2]	values[0x0]	100144793	1			T1	3150		T2	111195		T15	317
all_pins[2]	values[0x1]	302904	1			T2	5610		T7	498		T19	592
all_pins[2]	transitions[0x0=>0x1]	301116	1			T2	5572		T7	497		T19	592
all_pins[2]	transitions[0x1=>0x0]	507402	1			T1	293		T2	328		T15	10