Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	639	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5742	1			T1	27		T2	23		T7	13
len_601_800	12764	1			T1	70		T2	68		T6	4
len_401_600	8545	1			T1	56		T2	44		T7	23
len_201_400	16325	1			T1	27		T2	19		T30	251
len_65_200	73694	1			T1	11		T2	22		T30	680
len_min_for_xof_require_squeeze	1010	1			T1	1		T2	1		T30	10
len_keccak_block_sizes[72]	768	1			T30	5		T32	9		T36	1
len_keccak_block_sizes[104]	761	1			T30	5		T32	9		T195	9
len_keccak_block_sizes[136]	766	1			T30	5		T31	1		T32	9
len_keccak_block_sizes[144]	280	1			T30	5		T36	1		T52	5
len_keccak_block_sizes[168]	277	1			T1	1		T30	5		T52	5
len_datapath_width	14157	1			T1	1		T2	16		T15	3
len_2_63	213844	1			T1	6		T2	84		T15	6
len_1	75	1			T36	1		T75	1		T118	2