Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10879290 |
1 |
|
|
T1 |
32906 |
|
T2 |
31726 |
|
T15 |
96 |
auto[1] |
10879290 |
1 |
|
|
T1 |
32906 |
|
T2 |
31726 |
|
T15 |
96 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21519118 |
1 |
|
|
T1 |
65514 |
|
T2 |
63174 |
|
T15 |
192 |
triple_byte_access |
79524 |
1 |
|
|
T1 |
90 |
|
T2 |
82 |
|
T30 |
620 |
halfword_access |
80300 |
1 |
|
|
T1 |
90 |
|
T2 |
110 |
|
T30 |
632 |
byte_access |
79638 |
1 |
|
|
T1 |
118 |
|
T2 |
86 |
|
T30 |
620 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10759559 |
1 |
|
|
T1 |
32757 |
|
T2 |
31587 |
|
T15 |
96 |
auto[0] |
triple_byte_access |
39762 |
1 |
|
|
T1 |
45 |
|
T2 |
41 |
|
T30 |
310 |
auto[0] |
halfword_access |
40150 |
1 |
|
|
T1 |
45 |
|
T2 |
55 |
|
T30 |
316 |
auto[0] |
byte_access |
39819 |
1 |
|
|
T1 |
59 |
|
T2 |
43 |
|
T30 |
310 |
auto[1] |
word_access |
10759559 |
1 |
|
|
T1 |
32757 |
|
T2 |
31587 |
|
T15 |
96 |
auto[1] |
triple_byte_access |
39762 |
1 |
|
|
T1 |
45 |
|
T2 |
41 |
|
T30 |
310 |
auto[1] |
halfword_access |
40150 |
1 |
|
|
T1 |
45 |
|
T2 |
55 |
|
T30 |
316 |
auto[1] |
byte_access |
39819 |
1 |
|
|
T1 |
59 |
|
T2 |
43 |
|
T30 |
310 |