Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99115069	1			T2	114442		T3	225354		T18	460218
all_values[1]	99115069	1			T2	114442		T3	225354		T18	460218
all_values[2]	99115069	1			T2	114442		T3	225354		T18	460218

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

577659

1

T2

10

T18

3

T36

4396

auto[1]

296767548

1

T2

343316

T3

676062

T18

138065

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

295831860

1

T2

342234

T3

674361

T18

137043

auto[1]

1513347

1

T2

1092

T3

1701

T18

10218

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	232414	1			T18	1		T38	1		T39	1
all_values[0]	auto[0]	auto[1]	2119	1			T18	2		T38	2		T39	2
all_values[0]	auto[1]	auto[0]	98378206	1			T2	114078		T3	224787		T18	456811
all_values[0]	auto[1]	auto[1]	502330	1			T2	364		T3	567		T18	3404
all_values[1]	auto[0]	auto[0]	172351	1			T2	5		T36	2197		T38	1
all_values[1]	auto[0]	auto[1]	1583	1			T2	2		T36	1		T38	2
all_values[1]	auto[1]	auto[0]	98438269	1			T2	114073		T3	224787		T18	456812
all_values[1]	auto[1]	auto[1]	502866	1			T2	362		T3	567		T18	3406
all_values[2]	auto[0]	auto[0]	167558	1			T2	2		T36	2197		T39	4
all_values[2]	auto[0]	auto[1]	1634	1			T2	1		T36	1		T39	3
all_values[2]	auto[1]	auto[0]	98443062	1			T2	114076		T3	224787		T18	456812
all_values[2]	auto[1]	auto[1]	502815	1			T2	363		T3	567		T18	3406