Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99115069	1			T2	114442		T3	225354		T18	460218
all_pins[1]	99115069	1			T2	114442		T3	225354		T18	460218
all_pins[2]	99115069	1			T2	114442		T3	225354		T18	460218

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	296457054	1			T2	342962		T3	675495		T18	137725
values[0x1]	888153	1			T2	364		T3	567		T18	3404
transitions[0x0=>0x1]	885463	1			T2	364		T3	567		T18	3404
transitions[0x1=>0x0]	885481	1			T2	364		T3	567		T18	3404

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98612739	1			T2	114078		T3	224787		T18	456814
all_pins[0]	values[0x1]	502330	1			T2	364		T3	567		T18	3404
all_pins[0]	transitions[0x0=>0x1]	502316	1			T2	364		T3	567		T18	3404
all_pins[0]	transitions[0x1=>0x0]	5279	1			T8	12		T9	103		T24	9
all_pins[1]	values[0x0]	99109776	1			T2	114442		T3	225354		T18	460218
all_pins[1]	values[0x1]	5293	1			T8	12		T9	103		T24	9
all_pins[1]	transitions[0x0=>0x1]	4943	1			T8	12		T9	83		T24	9
all_pins[1]	transitions[0x1=>0x0]	380180	1			T8	8		T9	11115		T24	6
all_pins[2]	values[0x0]	98734539	1			T2	114442		T3	225354		T18	460218
all_pins[2]	values[0x1]	380530	1			T8	8		T9	11135		T24	6
all_pins[2]	transitions[0x0=>0x1]	378204	1			T8	8		T9	11067		T24	6
all_pins[2]	transitions[0x1=>0x0]	500022	1			T2	364		T3	567		T18	3404