Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10763915 |
1 |
|
|
T2 |
3936 |
|
T3 |
2730 |
|
T18 |
47900 |
auto[1] |
10763867 |
1 |
|
|
T2 |
3936 |
|
T3 |
2730 |
|
T18 |
47900 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21291942 |
1 |
|
|
T2 |
7872 |
|
T3 |
5460 |
|
T18 |
93928 |
triple_byte_access |
78362 |
1 |
|
|
T18 |
620 |
|
T23 |
24 |
|
T37 |
104 |
halfword_access |
79328 |
1 |
|
|
T18 |
632 |
|
T23 |
28 |
|
T37 |
94 |
byte_access |
78150 |
1 |
|
|
T18 |
620 |
|
T23 |
30 |
|
T37 |
92 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10645995 |
1 |
|
|
T2 |
3936 |
|
T3 |
2730 |
|
T18 |
46964 |
auto[0] |
triple_byte_access |
39181 |
1 |
|
|
T18 |
310 |
|
T23 |
12 |
|
T37 |
52 |
auto[0] |
halfword_access |
39664 |
1 |
|
|
T18 |
316 |
|
T23 |
14 |
|
T37 |
47 |
auto[0] |
byte_access |
39075 |
1 |
|
|
T18 |
310 |
|
T23 |
15 |
|
T37 |
46 |
auto[1] |
word_access |
10645947 |
1 |
|
|
T2 |
3936 |
|
T3 |
2730 |
|
T18 |
46964 |
auto[1] |
triple_byte_access |
39181 |
1 |
|
|
T18 |
310 |
|
T23 |
12 |
|
T37 |
52 |
auto[1] |
halfword_access |
39664 |
1 |
|
|
T18 |
316 |
|
T23 |
14 |
|
T37 |
47 |
auto[1] |
byte_access |
39075 |
1 |
|
|
T18 |
310 |
|
T23 |
15 |
|
T37 |
46 |