Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.59 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 2 16 88.89


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 2 16 88.89 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 269 1 T118 4 T119 7 T120 7
all_values[1] 269 1 T118 4 T119 7 T120 7
all_values[2] 269 1 T118 4 T119 7 T120 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 446 1 T118 6 T119 9 T120 5
auto[1] 361 1 T118 6 T119 12 T120 16


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 329 1 T118 7 T119 7 T120 7
auto[1] 478 1 T118 5 T119 14 T120 14


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 460 1 T118 7 T119 10 T120 9
auto[1] 347 1 T118 5 T119 11 T120 12


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 2 16 88.89 2
Automatically Generated Cross Bins 18 2 16 88.89 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[1]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 50 1 T118 1 T160 2 T161 1
all_values[0] auto[0] auto[0] auto[1] 31 1 T119 1 T160 1 T162 2
all_values[0] auto[0] auto[1] auto[0] 47 1 T118 3 T119 3 T120 1
all_values[0] auto[0] auto[1] auto[1] 26 1 T120 1 T163 1 T164 3
all_values[0] auto[1] auto[0] auto[1] 66 1 T119 3 T120 1 T160 2
all_values[0] auto[1] auto[1] auto[1] 49 1 T120 4 T160 2 T163 3
all_values[1] auto[0] auto[0] auto[0] 79 1 T118 1 T119 1 T120 1
all_values[1] auto[0] auto[1] auto[0] 77 1 T118 1 T119 2 T120 3
all_values[1] auto[1] auto[0] auto[1] 58 1 T118 1 T160 2 T162 2
all_values[1] auto[1] auto[1] auto[1] 55 1 T118 1 T119 4 T120 3
all_values[2] auto[0] auto[0] auto[0] 47 1 T118 1 T119 1 T120 1
all_values[2] auto[0] auto[0] auto[1] 40 1 T119 1 T120 1 T160 1
all_values[2] auto[0] auto[1] auto[0] 29 1 T120 1 T163 2 T162 1
all_values[2] auto[0] auto[1] auto[1] 34 1 T119 1 T160 2 T164 1
all_values[2] auto[1] auto[0] auto[1] 75 1 T118 2 T119 2 T120 1
all_values[2] auto[1] auto[1] auto[1] 44 1 T118 1 T119 2 T120 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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