Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100771866	1			T1	565050		T2	15059		T3	110397
all_values[1]	100771866	1			T1	565050		T2	15059		T3	110397
all_values[2]	100771866	1			T1	565050		T2	15059		T3	110397

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

539371

1

T1

3

T2

1

T3

18

auto[1]

301776227

1

T1

169514

T2

45176

T3

331173

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300787077

1

T1

168461

T2

44730

T3

330135

auto[1]

1528521

1

T1

10539

T2

447

T3

1056

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	161891	1			T2	1		T3	3		T7	1
all_values[0]	auto[0]	auto[1]	2015	1			T3	4		T35	2		T37	2
all_values[0]	auto[1]	auto[0]	100100468	1			T1	561537		T2	14909		T3	110042
all_values[0]	auto[1]	auto[1]	507492	1			T1	3513		T2	149		T3	348
all_values[1]	auto[0]	auto[0]	175818	1			T33	21		T7	3		T34	7
all_values[1]	auto[0]	auto[1]	1488	1			T33	9		T34	1		T35	2
all_values[1]	auto[1]	auto[0]	100086541	1			T1	561537		T2	14910		T3	110045
all_values[1]	auto[1]	auto[1]	508019	1			T1	3513		T2	149		T3	352
all_values[2]	auto[0]	auto[0]	196569	1			T1	2		T3	6		T33	7
all_values[2]	auto[0]	auto[1]	1590	1			T1	1		T3	5		T33	4
all_values[2]	auto[1]	auto[0]	100065790	1			T1	561535		T2	14910		T3	110039
all_values[2]	auto[1]	auto[1]	507917	1			T1	3512		T2	149		T3	347