Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
360866 |
1 |
|
|
T1 |
2 |
|
T2 |
324 |
|
T3 |
2 |
auto[1] |
331850 |
1 |
|
|
T1 |
4672 |
|
T3 |
490 |
|
T8 |
348 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173676 |
1 |
|
|
T1 |
1243 |
|
T2 |
90 |
|
T3 |
118 |
lower_val |
172086 |
1 |
|
|
T1 |
1180 |
|
T2 |
75 |
|
T3 |
147 |
zero_val |
1840 |
1 |
|
|
T1 |
9 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
263812 |
1 |
|
|
T1 |
1190 |
|
T2 |
152 |
|
T3 |
140 |
lower_val |
263096 |
1 |
|
|
T1 |
1160 |
|
T2 |
172 |
|
T3 |
120 |
zero_val |
165808 |
1 |
|
|
T1 |
2324 |
|
T3 |
232 |
|
T8 |
154 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
45487 |
1 |
|
|
T2 |
43 |
|
T33 |
84 |
|
T7 |
1 |
higher_val |
higher_val |
auto[1] |
20923 |
1 |
|
|
T1 |
311 |
|
T3 |
34 |
|
T8 |
25 |
higher_val |
lower_val |
auto[0] |
45409 |
1 |
|
|
T2 |
47 |
|
T33 |
86 |
|
T32 |
1 |
higher_val |
lower_val |
auto[1] |
20674 |
1 |
|
|
T1 |
307 |
|
T3 |
30 |
|
T8 |
23 |
higher_val |
zero_val |
auto[0] |
69 |
1 |
|
|
T34 |
1 |
|
T113 |
1 |
|
T38 |
1 |
higher_val |
zero_val |
auto[1] |
41114 |
1 |
|
|
T1 |
625 |
|
T3 |
54 |
|
T8 |
38 |
lower_val |
higher_val |
auto[0] |
44567 |
1 |
|
|
T1 |
1 |
|
T2 |
36 |
|
T33 |
75 |
lower_val |
higher_val |
auto[1] |
20828 |
1 |
|
|
T1 |
310 |
|
T3 |
44 |
|
T8 |
28 |
lower_val |
lower_val |
auto[0] |
44803 |
1 |
|
|
T2 |
39 |
|
T33 |
82 |
|
T7 |
1 |
lower_val |
lower_val |
auto[1] |
20655 |
1 |
|
|
T1 |
300 |
|
T3 |
36 |
|
T8 |
26 |
lower_val |
zero_val |
auto[0] |
90 |
1 |
|
|
T84 |
1 |
|
T85 |
1 |
|
T16 |
2 |
lower_val |
zero_val |
auto[1] |
41143 |
1 |
|
|
T1 |
569 |
|
T3 |
67 |
|
T8 |
46 |
zero_val |
higher_val |
auto[0] |
594 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T8 |
1 |
zero_val |
higher_val |
auto[1] |
126 |
1 |
|
|
T1 |
3 |
|
T81 |
4 |
|
T113 |
2 |
zero_val |
lower_val |
auto[0] |
567 |
1 |
|
|
T33 |
1 |
|
T7 |
1 |
|
T32 |
1 |
zero_val |
lower_val |
auto[1] |
121 |
1 |
|
|
T1 |
1 |
|
T81 |
1 |
|
T15 |
1 |
zero_val |
zero_val |
auto[0] |
240 |
1 |
|
|
T3 |
1 |
|
T34 |
1 |
|
T84 |
1 |
zero_val |
zero_val |
auto[1] |
192 |
1 |
|
|
T1 |
4 |
|
T81 |
3 |
|
T113 |
2 |