Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100771866	1			T1	565050		T2	15059		T3	110397
all_pins[1]	100771866	1			T1	565050		T2	15059		T3	110397
all_pins[2]	100771866	1			T1	565050		T2	15059		T3	110397

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	301487208	1			T1	169163		T2	45028		T3	330843
values[0x1]	828390	1			T1	3513		T2	149		T3	348
transitions[0x0=>0x1]	826281	1			T1	3513		T2	149		T3	348
transitions[0x1=>0x0]	826298	1			T1	3513		T2	149		T3	348

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100264374	1			T1	561537		T2	14910		T3	110049
all_pins[0]	values[0x1]	507492	1			T1	3513		T2	149		T3	348
all_pins[0]	transitions[0x0=>0x1]	507481	1			T1	3513		T2	149		T3	348
all_pins[0]	transitions[0x1=>0x0]	6455	1			T8	15		T32	70		T36	52
all_pins[1]	values[0x0]	100765400	1			T1	565050		T2	15059		T3	110397
all_pins[1]	values[0x1]	6466	1			T8	15		T32	70		T36	52
all_pins[1]	transitions[0x0=>0x1]	6255	1			T8	15		T32	70		T36	52
all_pins[1]	transitions[0x1=>0x0]	314221	1			T21	2117		T19	559		T42	321
all_pins[2]	values[0x0]	100457434	1			T1	565050		T2	15059		T3	110397
all_pins[2]	values[0x1]	314432	1			T21	2117		T19	559		T42	321
all_pins[2]	transitions[0x0=>0x1]	312545	1			T21	2116		T19	559		T42	321
all_pins[2]	transitions[0x1=>0x0]	505622	1			T1	3513		T2	149		T3	348