Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10490098 |
1 |
|
|
T1 |
27235 |
|
T2 |
19013 |
|
T3 |
3936 |
auto[1] |
10490046 |
1 |
|
|
T1 |
27235 |
|
T2 |
19013 |
|
T3 |
3936 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
20743142 |
1 |
|
|
T1 |
52796 |
|
T2 |
37896 |
|
T3 |
7872 |
triple_byte_access |
78382 |
1 |
|
|
T1 |
558 |
|
T2 |
28 |
|
T7 |
2 |
halfword_access |
79604 |
1 |
|
|
T1 |
558 |
|
T2 |
64 |
|
T8 |
58 |
byte_access |
79016 |
1 |
|
|
T1 |
558 |
|
T2 |
38 |
|
T7 |
4 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10371597 |
1 |
|
|
T1 |
26398 |
|
T2 |
18948 |
|
T3 |
3936 |
auto[0] |
triple_byte_access |
39191 |
1 |
|
|
T1 |
279 |
|
T2 |
14 |
|
T7 |
1 |
auto[0] |
halfword_access |
39802 |
1 |
|
|
T1 |
279 |
|
T2 |
32 |
|
T8 |
29 |
auto[0] |
byte_access |
39508 |
1 |
|
|
T1 |
279 |
|
T2 |
19 |
|
T7 |
2 |
auto[1] |
word_access |
10371545 |
1 |
|
|
T1 |
26398 |
|
T2 |
18948 |
|
T3 |
3936 |
auto[1] |
triple_byte_access |
39191 |
1 |
|
|
T1 |
279 |
|
T2 |
14 |
|
T7 |
1 |
auto[1] |
halfword_access |
39802 |
1 |
|
|
T1 |
279 |
|
T2 |
32 |
|
T8 |
29 |
auto[1] |
byte_access |
39508 |
1 |
|
|
T1 |
279 |
|
T2 |
19 |
|
T7 |
2 |