Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99143360	1			T2	92446		T3	20047		T7	5607
all_values[1]	99143360	1			T2	92446		T3	20047		T7	5607
all_values[2]	99143360	1			T2	92446		T3	20047		T7	5607

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

540675

1

T2

12789

T3

186

T7

459

auto[1]

296889405

1

T2

264549

T3

59955

T7

16362

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

295913496

1

T2

276561

T3

59574

T7

16596

auto[1]

1516584

1

T2

777

T3

567

T7

225

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	181349	1			T2	6409		T7	363		T18	529
all_values[0]	auto[0]	auto[1]	2087	1			T2	20		T7	10		T18	24
all_values[0]	auto[1]	auto[0]	98456483	1			T2	85778		T3	19858		T7	5169
all_values[0]	auto[1]	auto[1]	503441	1			T2	239		T3	189		T7	65
all_values[1]	auto[0]	auto[0]	175396	1			T2	6276		T7	45		T17	1
all_values[1]	auto[0]	auto[1]	1623	1			T2	6		T7	4		T29	3
all_values[1]	auto[1]	auto[0]	98462436	1			T2	85911		T3	19858		T7	5487
all_values[1]	auto[1]	auto[1]	503905	1			T2	253		T3	189		T7	71
all_values[2]	auto[0]	auto[0]	178639	1			T2	73		T3	185		T7	33
all_values[2]	auto[0]	auto[1]	1581	1			T2	5		T3	1		T7	4
all_values[2]	auto[1]	auto[0]	98459193	1			T2	92114		T3	19673		T7	5499
all_values[2]	auto[1]	auto[1]	503947	1			T2	254		T3	188		T7	71