Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
381630 |
1 |
|
|
T2 |
190 |
|
T3 |
338 |
|
T7 |
112 |
auto[1] |
305356 |
1 |
|
|
T2 |
200 |
|
T7 |
18 |
|
T29 |
154 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
172035 |
1 |
|
|
T2 |
87 |
|
T3 |
98 |
|
T7 |
36 |
lower_val |
170786 |
1 |
|
|
T2 |
85 |
|
T3 |
75 |
|
T7 |
27 |
zero_val |
1808 |
1 |
|
|
T2 |
5 |
|
T3 |
1 |
|
T7 |
5 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
266500 |
1 |
|
|
T2 |
122 |
|
T3 |
158 |
|
T7 |
52 |
lower_val |
267362 |
1 |
|
|
T2 |
168 |
|
T3 |
180 |
|
T7 |
76 |
zero_val |
153124 |
1 |
|
|
T2 |
100 |
|
T7 |
2 |
|
T29 |
68 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
47647 |
1 |
|
|
T2 |
15 |
|
T3 |
50 |
|
T7 |
16 |
higher_val |
higher_val |
auto[1] |
19139 |
1 |
|
|
T2 |
11 |
|
T29 |
5 |
|
T18 |
14 |
higher_val |
lower_val |
auto[0] |
48064 |
1 |
|
|
T2 |
19 |
|
T3 |
48 |
|
T7 |
18 |
higher_val |
lower_val |
auto[1] |
19008 |
1 |
|
|
T2 |
14 |
|
T7 |
2 |
|
T29 |
9 |
higher_val |
zero_val |
auto[0] |
82 |
1 |
|
|
T29 |
1 |
|
T18 |
1 |
|
T106 |
1 |
higher_val |
zero_val |
auto[1] |
38095 |
1 |
|
|
T2 |
28 |
|
T29 |
14 |
|
T18 |
43 |
lower_val |
higher_val |
auto[0] |
47131 |
1 |
|
|
T2 |
23 |
|
T3 |
28 |
|
T7 |
12 |
lower_val |
higher_val |
auto[1] |
19026 |
1 |
|
|
T2 |
10 |
|
T29 |
10 |
|
T18 |
20 |
lower_val |
lower_val |
auto[0] |
47642 |
1 |
|
|
T2 |
18 |
|
T3 |
47 |
|
T7 |
13 |
lower_val |
lower_val |
auto[1] |
18969 |
1 |
|
|
T2 |
13 |
|
T7 |
2 |
|
T29 |
6 |
lower_val |
zero_val |
auto[0] |
69 |
1 |
|
|
T18 |
1 |
|
T168 |
1 |
|
T23 |
1 |
lower_val |
zero_val |
auto[1] |
37949 |
1 |
|
|
T2 |
21 |
|
T29 |
16 |
|
T18 |
46 |
zero_val |
higher_val |
auto[0] |
613 |
1 |
|
|
T2 |
2 |
|
T3 |
1 |
|
T7 |
2 |
zero_val |
higher_val |
auto[1] |
107 |
1 |
|
|
T7 |
1 |
|
T31 |
1 |
|
T34 |
1 |
zero_val |
lower_val |
auto[0] |
546 |
1 |
|
|
T2 |
1 |
|
T7 |
1 |
|
T17 |
1 |
zero_val |
lower_val |
auto[1] |
117 |
1 |
|
|
T2 |
1 |
|
T18 |
2 |
|
T31 |
2 |
zero_val |
zero_val |
auto[0] |
252 |
1 |
|
|
T2 |
1 |
|
T7 |
1 |
|
T29 |
1 |
zero_val |
zero_val |
auto[1] |
173 |
1 |
|
|
T18 |
1 |
|
T31 |
1 |
|
T34 |
2 |