Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99143360	1			T2	92446		T3	20047		T7	5607
all_pins[1]	99143360	1			T2	92446		T3	20047		T7	5607
all_pins[2]	99143360	1			T2	92446		T3	20047		T7	5607

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	296600113	1			T2	274442		T3	40216		T7	15304
values[0x1]	829967	1			T2	2896		T3	19925		T7	1517
transitions[0x0=>0x1]	827701	1			T2	2874		T3	19801		T7	1503
transitions[0x1=>0x0]	827726	1			T2	2874		T3	19801		T7	1503

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98639919	1			T2	92207		T3	19858		T7	5542
all_pins[0]	values[0x1]	503441	1			T2	239		T3	189		T7	65
all_pins[0]	transitions[0x0=>0x1]	503429	1			T2	239		T3	189		T7	65
all_pins[0]	transitions[0x1=>0x0]	6131	1			T2	43		T7	17		T18	91
all_pins[1]	values[0x0]	99137217	1			T2	92403		T3	20047		T7	5590
all_pins[1]	values[0x1]	6143	1			T2	43		T7	17		T18	91
all_pins[1]	transitions[0x0=>0x1]	5868	1			T2	39		T7	10		T18	75
all_pins[1]	transitions[0x1=>0x0]	320108	1			T2	2610		T3	19736		T7	1428
all_pins[2]	values[0x0]	98822977	1			T2	89832		T3	311		T7	4172
all_pins[2]	values[0x1]	320383	1			T2	2614		T3	19736		T7	1435
all_pins[2]	transitions[0x0=>0x1]	318404	1			T2	2596		T3	19612		T7	1428
all_pins[2]	transitions[0x1=>0x0]	501487	1			T2	221		T3	65		T7	58