Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10498715 |
1 |
|
|
T2 |
22052 |
|
T3 |
21870 |
|
T7 |
6936 |
auto[1] |
10498696 |
1 |
|
|
T2 |
22052 |
|
T3 |
21870 |
|
T7 |
6936 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
20761903 |
1 |
|
|
T2 |
43854 |
|
T3 |
43546 |
|
T7 |
13810 |
triple_byte_access |
78192 |
1 |
|
|
T2 |
52 |
|
T3 |
82 |
|
T7 |
24 |
halfword_access |
78906 |
1 |
|
|
T2 |
106 |
|
T3 |
58 |
|
T7 |
24 |
byte_access |
78410 |
1 |
|
|
T2 |
92 |
|
T3 |
54 |
|
T7 |
14 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10380961 |
1 |
|
|
T2 |
21927 |
|
T3 |
21773 |
|
T7 |
6905 |
auto[0] |
triple_byte_access |
39096 |
1 |
|
|
T2 |
26 |
|
T3 |
41 |
|
T7 |
12 |
auto[0] |
halfword_access |
39453 |
1 |
|
|
T2 |
53 |
|
T3 |
29 |
|
T7 |
12 |
auto[0] |
byte_access |
39205 |
1 |
|
|
T2 |
46 |
|
T3 |
27 |
|
T7 |
7 |
auto[1] |
word_access |
10380942 |
1 |
|
|
T2 |
21927 |
|
T3 |
21773 |
|
T7 |
6905 |
auto[1] |
triple_byte_access |
39096 |
1 |
|
|
T2 |
26 |
|
T3 |
41 |
|
T7 |
12 |
auto[1] |
halfword_access |
39453 |
1 |
|
|
T2 |
53 |
|
T3 |
29 |
|
T7 |
12 |
auto[1] |
byte_access |
39205 |
1 |
|
|
T2 |
46 |
|
T3 |
27 |
|
T7 |
7 |