Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.59 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 2 16 88.89


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 2 16 88.89 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 287 1 T114 7 T115 4 T116 7
all_values[1] 287 1 T114 7 T115 4 T116 7
all_values[2] 287 1 T114 7 T115 4 T116 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 493 1 T114 12 T115 10 T116 12
auto[1] 368 1 T114 9 T115 2 T116 9


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 403 1 T114 10 T115 7 T116 15
auto[1] 458 1 T114 11 T115 5 T116 6


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 527 1 T114 12 T115 9 T116 17
auto[1] 334 1 T114 9 T115 3 T116 4


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 2 16 88.89 2
Automatically Generated Cross Bins 18 2 16 88.89 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[1]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 68 1 T114 2 T116 2 T142 1
all_values[0] auto[0] auto[0] auto[1] 36 1 T115 2 T142 1 T147 2
all_values[0] auto[0] auto[1] auto[0] 44 1 T114 2 T116 3 T142 1
all_values[0] auto[0] auto[1] auto[1] 31 1 T116 1 T147 1 T148 1
all_values[0] auto[1] auto[0] auto[1] 69 1 T114 1 T115 2 T116 1
all_values[0] auto[1] auto[1] auto[1] 39 1 T114 2 T147 1 T149 2
all_values[1] auto[0] auto[0] auto[0] 101 1 T114 4 T115 2 T116 3
all_values[1] auto[0] auto[1] auto[0] 79 1 T115 1 T116 2 T142 1
all_values[1] auto[1] auto[0] auto[1] 66 1 T114 1 T116 1 T142 1
all_values[1] auto[1] auto[1] auto[1] 41 1 T114 2 T115 1 T116 1
all_values[2] auto[0] auto[0] auto[0] 61 1 T114 1 T115 4 T116 4
all_values[2] auto[0] auto[0] auto[1] 22 1 T148 1 T149 1 T150 2
all_values[2] auto[0] auto[1] auto[0] 50 1 T114 1 T116 1 T147 1
all_values[2] auto[0] auto[1] auto[1] 35 1 T114 2 T116 1 T142 1
all_values[2] auto[1] auto[0] auto[1] 70 1 T114 3 T116 1 T142 1
all_values[2] auto[1] auto[1] auto[1] 49 1 T142 1 T147 1 T148 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%