Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 7 0 7 100.00
Crosses 12 0 12 100.00


Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_cg_cc 12 0 12 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 98948071 1 T1 264060 T2 221752 T16 568366
all_values[1] 98948071 1 T1 264060 T2 221752 T16 568366
all_values[2] 98948071 1 T1 264060 T2 221752 T16 568366



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 600332 1 T2 13 T16 6 T33 89
auto[1] 296243881 1 T1 792180 T2 665243 T16 170509



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 295322943 1 T1 791448 T2 663549 T16 169463
auto[1] 1521270 1 T1 732 T2 1707 T16 10461



Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 12 0 12 100.00


Automatically Generated Cross Bins for intr_cg_cc

Bins
cp_intrcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] 165314 1 T2 1 T16 1 T33 81
all_values[0] auto[0] auto[1] 2160 1 T2 2 T16 2 T33 8
all_values[0] auto[1] auto[0] 98275667 1 T1 263816 T2 221182 T16 564878
all_values[0] auto[1] auto[1] 504930 1 T1 244 T2 567 T16 3485
all_values[1] auto[0] auto[0] 234003 1 T2 1 T34 26 T7 107
all_values[1] auto[0] auto[1] 1647 1 T2 2 T34 1 T7 3
all_values[1] auto[1] auto[0] 98206978 1 T1 263816 T2 221182 T16 564879
all_values[1] auto[1] auto[1] 505443 1 T1 244 T2 567 T16 3487
all_values[2] auto[0] auto[0] 195683 1 T2 4 T16 1 T7 114
all_values[2] auto[0] auto[1] 1525 1 T2 3 T16 2 T7 7
all_values[2] auto[1] auto[0] 98245298 1 T1 263816 T2 221179 T16 564878
all_values[2] auto[1] auto[1] 505565 1 T1 244 T2 566 T16 3485

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