Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
347550 |
1 |
|
|
T1 |
346 |
|
T2 |
2 |
|
T16 |
4674 |
auto[1] |
342532 |
1 |
|
|
T2 |
778 |
|
T35 |
778 |
|
T34 |
102 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
172453 |
1 |
|
|
T1 |
70 |
|
T2 |
198 |
|
T16 |
1179 |
lower_val |
171818 |
1 |
|
|
T1 |
112 |
|
T2 |
182 |
|
T16 |
1130 |
zero_val |
1890 |
1 |
|
|
T1 |
1 |
|
T2 |
5 |
|
T16 |
7 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
258452 |
1 |
|
|
T1 |
178 |
|
T2 |
188 |
|
T16 |
2306 |
lower_val |
259508 |
1 |
|
|
T1 |
168 |
|
T2 |
190 |
|
T16 |
2368 |
zero_val |
172122 |
1 |
|
|
T2 |
402 |
|
T35 |
396 |
|
T34 |
64 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
43163 |
1 |
|
|
T1 |
33 |
|
T16 |
573 |
|
T7 |
26 |
higher_val |
higher_val |
auto[1] |
21337 |
1 |
|
|
T2 |
46 |
|
T35 |
61 |
|
T34 |
4 |
higher_val |
lower_val |
auto[0] |
43619 |
1 |
|
|
T1 |
37 |
|
T16 |
606 |
|
T35 |
1 |
higher_val |
lower_val |
auto[1] |
21422 |
1 |
|
|
T2 |
60 |
|
T35 |
46 |
|
T7 |
12 |
higher_val |
zero_val |
auto[0] |
86 |
1 |
|
|
T9 |
2 |
|
T39 |
1 |
|
T62 |
1 |
higher_val |
zero_val |
auto[1] |
42826 |
1 |
|
|
T2 |
92 |
|
T35 |
97 |
|
T34 |
16 |
lower_val |
higher_val |
auto[0] |
43227 |
1 |
|
|
T1 |
51 |
|
T16 |
556 |
|
T33 |
2 |
lower_val |
higher_val |
auto[1] |
21012 |
1 |
|
|
T2 |
47 |
|
T35 |
48 |
|
T34 |
5 |
lower_val |
lower_val |
auto[0] |
42980 |
1 |
|
|
T1 |
61 |
|
T16 |
574 |
|
T33 |
3 |
lower_val |
lower_val |
auto[1] |
21596 |
1 |
|
|
T2 |
45 |
|
T35 |
58 |
|
T34 |
7 |
lower_val |
zero_val |
auto[0] |
88 |
1 |
|
|
T63 |
1 |
|
T64 |
1 |
|
T20 |
1 |
lower_val |
zero_val |
auto[1] |
42915 |
1 |
|
|
T2 |
90 |
|
T35 |
100 |
|
T34 |
16 |
zero_val |
higher_val |
auto[0] |
592 |
1 |
|
|
T1 |
1 |
|
T16 |
2 |
|
T7 |
1 |
zero_val |
higher_val |
auto[1] |
138 |
1 |
|
|
T2 |
1 |
|
T7 |
1 |
|
T8 |
1 |
zero_val |
lower_val |
auto[0] |
558 |
1 |
|
|
T16 |
5 |
|
T33 |
1 |
|
T35 |
1 |
zero_val |
lower_val |
auto[1] |
159 |
1 |
|
|
T2 |
3 |
|
T35 |
1 |
|
T7 |
1 |
zero_val |
zero_val |
auto[0] |
250 |
1 |
|
|
T2 |
1 |
|
T34 |
1 |
|
T8 |
3 |
zero_val |
zero_val |
auto[1] |
193 |
1 |
|
|
T35 |
1 |
|
T8 |
2 |
|
T39 |
1 |