Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	98948071	1			T1	264060		T2	221752		T16	568366
all_pins[1]	98948071	1			T1	264060		T2	221752		T16	568366
all_pins[2]	98948071	1			T1	264060		T2	221752		T16	568366

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	296028864	1			T1	791936		T2	664689		T16	170161
values[0x1]	815349	1			T1	244		T2	567		T16	3485
transitions[0x0=>0x1]	813031	1			T1	244		T2	567		T16	3485
transitions[0x1=>0x0]	813051	1			T1	244		T2	567		T16	3485

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98443141	1			T1	263816		T2	221185		T16	564881
all_pins[0]	values[0x1]	504930	1			T1	244		T2	567		T16	3485
all_pins[0]	transitions[0x0=>0x1]	504906	1			T1	244		T2	567		T16	3485
all_pins[0]	transitions[0x1=>0x0]	6110	1			T33	1		T63	107		T91	8
all_pins[1]	values[0x0]	98941937	1			T1	264060		T2	221752		T16	568366
all_pins[1]	values[0x1]	6134	1			T33	1		T63	107		T91	8
all_pins[1]	transitions[0x0=>0x1]	5765	1			T33	1		T63	107		T91	8
all_pins[1]	transitions[0x1=>0x0]	303916	1			T7	2829		T8	4464		T9	387
all_pins[2]	values[0x0]	98643786	1			T1	264060		T2	221752		T16	568366
all_pins[2]	values[0x1]	304285	1			T7	2829		T8	4464		T9	387
all_pins[2]	transitions[0x0=>0x1]	302360	1			T7	2813		T8	4433		T9	386
all_pins[2]	transitions[0x1=>0x0]	503025	1			T1	244		T2	567		T16	3485