Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	663	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5583	1			T1	28		T34	4		T7	13
len_601_800	12949	1			T1	63		T34	25		T7	47
len_401_600	8556	1			T1	35		T34	11		T7	21
len_201_400	16398	1			T1	26		T34	4		T7	14
len_65_200	73537	1			T1	10		T16	685		T34	3
len_min_for_xof_require_squeeze	997	1			T16	9		T62	10		T168	1
len_keccak_block_sizes[72]	750	1			T16	9		T62	5		T64	1
len_keccak_block_sizes[104]	753	1			T16	9		T62	5		T169	9
len_keccak_block_sizes[136]	758	1			T16	9		T62	5		T170	1
len_keccak_block_sizes[144]	285	1			T9	1		T62	5		T170	1
len_keccak_block_sizes[168]	271	1			T1	1		T62	5		T91	1
len_datapath_width	13966	1			T1	1		T16	9		T33	3
len_2_63	211923	1			T1	6		T2	390		T16	1643
len_1	42	1			T170	1		T171	1		T18	1