Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10829880 |
1 |
|
|
T1 |
28761 |
|
T2 |
2730 |
|
T16 |
27235 |
auto[1] |
10829880 |
1 |
|
|
T1 |
28761 |
|
T2 |
2730 |
|
T16 |
27235 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21421638 |
1 |
|
|
T1 |
57270 |
|
T2 |
5460 |
|
T16 |
52796 |
triple_byte_access |
79280 |
1 |
|
|
T1 |
84 |
|
T16 |
558 |
|
T34 |
24 |
halfword_access |
79744 |
1 |
|
|
T1 |
84 |
|
T16 |
558 |
|
T34 |
18 |
byte_access |
79098 |
1 |
|
|
T1 |
84 |
|
T16 |
558 |
|
T34 |
30 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10710819 |
1 |
|
|
T1 |
28635 |
|
T2 |
2730 |
|
T16 |
26398 |
auto[0] |
triple_byte_access |
39640 |
1 |
|
|
T1 |
42 |
|
T16 |
279 |
|
T34 |
12 |
auto[0] |
halfword_access |
39872 |
1 |
|
|
T1 |
42 |
|
T16 |
279 |
|
T34 |
9 |
auto[0] |
byte_access |
39549 |
1 |
|
|
T1 |
42 |
|
T16 |
279 |
|
T34 |
15 |
auto[1] |
word_access |
10710819 |
1 |
|
|
T1 |
28635 |
|
T2 |
2730 |
|
T16 |
26398 |
auto[1] |
triple_byte_access |
39640 |
1 |
|
|
T1 |
42 |
|
T16 |
279 |
|
T34 |
12 |
auto[1] |
halfword_access |
39872 |
1 |
|
|
T1 |
42 |
|
T16 |
279 |
|
T34 |
9 |
auto[1] |
byte_access |
39549 |
1 |
|
|
T1 |
42 |
|
T16 |
279 |
|
T34 |
15 |