Group : kmac_env_pkg::kmac_env_cov::state_read_mask_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : kmac_env_pkg::kmac_env_cov::state_read_mask_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv



Summary for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 8 0 8 100.00


Variables for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
share 2 0 2 100.00 100 1 1 2
state_read_mask 4 0 4 100.00 100 1 1 0


Crosses for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
state_mask_share_cross 8 0 8 100.00 100 1 1 0


Summary for Variable share

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for share

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 10829880 1 T1 28761 T2 2730 T16 27235
auto[1] 10829880 1 T1 28761 T2 2730 T16 27235



Summary for Variable state_read_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for state_read_mask

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
word_access 21421638 1 T1 57270 T2 5460 T16 52796
triple_byte_access 79280 1 T1 84 T16 558 T34 24
halfword_access 79744 1 T1 84 T16 558 T34 18
byte_access 79098 1 T1 84 T16 558 T34 30



Summary for Cross state_mask_share_cross

Samples crossed: share state_read_mask
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for state_mask_share_cross

Bins
sharestate_read_maskCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] word_access 10710819 1 T1 28635 T2 2730 T16 26398
auto[0] triple_byte_access 39640 1 T1 42 T16 279 T34 12
auto[0] halfword_access 39872 1 T1 42 T16 279 T34 9
auto[0] byte_access 39549 1 T1 42 T16 279 T34 15
auto[1] word_access 10710819 1 T1 28635 T2 2730 T16 26398
auto[1] triple_byte_access 39640 1 T1 42 T16 279 T34 12
auto[1] halfword_access 39872 1 T1 42 T16 279 T34 9
auto[1] byte_access 39549 1 T1 42 T16 279 T34 15

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%