Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.05 97.89 92.58 99.54 76.06 95.53 98.88 97.88


Total test records in report: 1235
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T1046 /workspace/coverage/default/3.kmac_test_vectors_shake_256.4165397733 May 21 12:53:20 PM PDT 24 May 21 02:17:03 PM PDT 24 796358555305 ps
T1047 /workspace/coverage/default/47.kmac_sideload.2353279359 May 21 01:00:02 PM PDT 24 May 21 01:02:59 PM PDT 24 15359320108 ps
T1048 /workspace/coverage/default/26.kmac_long_msg_and_output.1680499764 May 21 12:55:13 PM PDT 24 May 21 01:25:05 PM PDT 24 69485555239 ps
T1049 /workspace/coverage/default/43.kmac_smoke.2631227957 May 21 12:58:38 PM PDT 24 May 21 01:00:04 PM PDT 24 6154854381 ps
T1050 /workspace/coverage/default/27.kmac_test_vectors_sha3_512.2845381442 May 21 12:55:11 PM PDT 24 May 21 01:14:28 PM PDT 24 12830549073 ps
T1051 /workspace/coverage/default/37.kmac_test_vectors_sha3_384.2333427488 May 21 12:56:59 PM PDT 24 May 21 01:27:07 PM PDT 24 534105678615 ps
T1052 /workspace/coverage/default/41.kmac_burst_write.4223439118 May 21 12:58:03 PM PDT 24 May 21 12:58:45 PM PDT 24 1208871279 ps
T1053 /workspace/coverage/default/26.kmac_test_vectors_kmac_xof.1287627309 May 21 12:55:05 PM PDT 24 May 21 12:55:13 PM PDT 24 224222921 ps
T1054 /workspace/coverage/default/14.kmac_test_vectors_sha3_384.2399998171 May 21 12:54:14 PM PDT 24 May 21 01:21:44 PM PDT 24 49379436707 ps
T1055 /workspace/coverage/default/6.kmac_test_vectors_sha3_384.2500057944 May 21 12:53:52 PM PDT 24 May 21 01:22:55 PM PDT 24 77283361369 ps
T1056 /workspace/coverage/default/39.kmac_error.2676700850 May 21 12:57:32 PM PDT 24 May 21 01:03:20 PM PDT 24 11650761509 ps
T1057 /workspace/coverage/default/48.kmac_long_msg_and_output.2129131224 May 21 01:00:26 PM PDT 24 May 21 01:47:51 PM PDT 24 118926959150 ps
T1058 /workspace/coverage/default/14.kmac_test_vectors_sha3_224.4085169695 May 21 12:54:06 PM PDT 24 May 21 01:29:58 PM PDT 24 63086254169 ps
T1059 /workspace/coverage/default/7.kmac_test_vectors_sha3_512.44878539 May 21 12:54:04 PM PDT 24 May 21 01:14:50 PM PDT 24 35031370062 ps
T1060 /workspace/coverage/default/12.kmac_test_vectors_kmac.3913275104 May 21 12:53:54 PM PDT 24 May 21 12:54:04 PM PDT 24 206297981 ps
T1061 /workspace/coverage/default/45.kmac_smoke.2485650 May 21 12:59:19 PM PDT 24 May 21 12:59:24 PM PDT 24 122207600 ps
T1062 /workspace/coverage/default/17.kmac_alert_test.3908728454 May 21 12:54:14 PM PDT 24 May 21 12:54:19 PM PDT 24 48313645 ps
T1063 /workspace/coverage/default/2.kmac_test_vectors_sha3_224.653580620 May 21 12:53:49 PM PDT 24 May 21 01:35:30 PM PDT 24 392187598464 ps
T1064 /workspace/coverage/default/20.kmac_app.174469164 May 21 12:54:25 PM PDT 24 May 21 12:55:49 PM PDT 24 10674484654 ps
T1065 /workspace/coverage/default/32.kmac_alert_test.2637692800 May 21 12:56:00 PM PDT 24 May 21 12:56:01 PM PDT 24 93908107 ps
T1066 /workspace/coverage/default/33.kmac_smoke.2970368879 May 21 12:56:02 PM PDT 24 May 21 12:56:28 PM PDT 24 653694087 ps
T1067 /workspace/coverage/default/13.kmac_test_vectors_shake_128.2431485179 May 21 12:54:12 PM PDT 24 May 21 02:34:30 PM PDT 24 520256272364 ps
T1068 /workspace/coverage/default/46.kmac_entropy_refresh.635713324 May 21 12:59:54 PM PDT 24 May 21 01:03:41 PM PDT 24 51545042344 ps
T1069 /workspace/coverage/default/46.kmac_long_msg_and_output.1020168305 May 21 12:59:43 PM PDT 24 May 21 01:36:39 PM PDT 24 65684307715 ps
T1070 /workspace/coverage/default/30.kmac_test_vectors_sha3_512.3598784669 May 21 12:55:33 PM PDT 24 May 21 01:14:49 PM PDT 24 21503969449 ps
T81 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.869202378 May 21 01:55:57 PM PDT 24 May 21 01:55:59 PM PDT 24 300841553 ps
T167 /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.2436165222 May 21 01:55:58 PM PDT 24 May 21 01:56:08 PM PDT 24 386429205 ps
T113 /workspace/coverage/cover_reg_top/33.kmac_intr_test.890451206 May 21 01:56:39 PM PDT 24 May 21 01:56:41 PM PDT 24 151720436 ps
T130 /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.3463823071 May 21 01:56:30 PM PDT 24 May 21 01:56:34 PM PDT 24 90327326 ps
T1071 /workspace/coverage/cover_reg_top/9.kmac_tl_errors.3022807492 May 21 01:56:14 PM PDT 24 May 21 01:56:17 PM PDT 24 85322363 ps
T1072 /workspace/coverage/cover_reg_top/16.kmac_tl_errors.575777661 May 21 01:56:33 PM PDT 24 May 21 01:56:38 PM PDT 24 58820543 ps
T131 /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.3156622455 May 21 01:56:08 PM PDT 24 May 21 01:56:11 PM PDT 24 149655617 ps
T132 /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.2729256265 May 21 01:55:55 PM PDT 24 May 21 01:56:07 PM PDT 24 1921345634 ps
T84 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.4029302223 May 21 01:56:00 PM PDT 24 May 21 01:56:02 PM PDT 24 18367733 ps
T1073 /workspace/coverage/cover_reg_top/4.kmac_tl_errors.1973385343 May 21 01:56:06 PM PDT 24 May 21 01:56:09 PM PDT 24 101682632 ps
T1074 /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.2667743759 May 21 01:55:59 PM PDT 24 May 21 01:56:02 PM PDT 24 1179808115 ps
T1075 /workspace/coverage/cover_reg_top/13.kmac_csr_rw.2301474267 May 21 01:56:32 PM PDT 24 May 21 01:56:34 PM PDT 24 115156074 ps
T114 /workspace/coverage/cover_reg_top/18.kmac_intr_test.44489963 May 21 01:56:35 PM PDT 24 May 21 01:56:37 PM PDT 24 27742101 ps
T110 /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.4229023457 May 21 01:55:58 PM PDT 24 May 21 01:56:02 PM PDT 24 177071769 ps
T115 /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.4076564658 May 21 01:56:03 PM PDT 24 May 21 01:56:05 PM PDT 24 31485861 ps
T133 /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.3386817286 May 21 01:56:29 PM PDT 24 May 21 01:56:33 PM PDT 24 179159034 ps
T149 /workspace/coverage/cover_reg_top/23.kmac_intr_test.2142151021 May 21 01:56:36 PM PDT 24 May 21 01:56:40 PM PDT 24 41904681 ps
T111 /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.1329541809 May 21 01:56:19 PM PDT 24 May 21 01:56:25 PM PDT 24 190298807 ps
T82 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.98203085 May 21 01:56:08 PM PDT 24 May 21 01:56:10 PM PDT 24 97734892 ps
T150 /workspace/coverage/cover_reg_top/17.kmac_intr_test.302623715 May 21 01:56:30 PM PDT 24 May 21 01:56:33 PM PDT 24 22186905 ps
T1076 /workspace/coverage/cover_reg_top/18.kmac_csr_rw.2101812168 May 21 01:56:34 PM PDT 24 May 21 01:56:36 PM PDT 24 42800156 ps
T86 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2551504972 May 21 01:56:29 PM PDT 24 May 21 01:56:32 PM PDT 24 45359061 ps
T1077 /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.4173241810 May 21 01:55:55 PM PDT 24 May 21 01:56:17 PM PDT 24 3356932131 ps
T134 /workspace/coverage/cover_reg_top/15.kmac_csr_rw.4135207798 May 21 01:56:29 PM PDT 24 May 21 01:56:33 PM PDT 24 330763046 ps
T83 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.4139081545 May 21 01:56:33 PM PDT 24 May 21 01:56:36 PM PDT 24 44145949 ps
T151 /workspace/coverage/cover_reg_top/40.kmac_intr_test.1615103177 May 21 01:56:42 PM PDT 24 May 21 01:56:46 PM PDT 24 87711021 ps
T1078 /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.1905460032 May 21 01:56:36 PM PDT 24 May 21 01:56:40 PM PDT 24 31393223 ps
T152 /workspace/coverage/cover_reg_top/1.kmac_intr_test.3150533401 May 21 01:55:56 PM PDT 24 May 21 01:55:58 PM PDT 24 19132223 ps
T135 /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.4293991581 May 21 01:56:28 PM PDT 24 May 21 01:56:33 PM PDT 24 183446577 ps
T146 /workspace/coverage/cover_reg_top/6.kmac_csr_rw.1700431654 May 21 01:56:12 PM PDT 24 May 21 01:56:13 PM PDT 24 22295916 ps
T112 /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.1918341351 May 21 01:56:23 PM PDT 24 May 21 01:56:30 PM PDT 24 391138823 ps
T153 /workspace/coverage/cover_reg_top/22.kmac_intr_test.1022586057 May 21 01:56:37 PM PDT 24 May 21 01:56:40 PM PDT 24 13631119 ps
T1079 /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3098727652 May 21 01:56:17 PM PDT 24 May 21 01:56:20 PM PDT 24 53672796 ps
T1080 /workspace/coverage/cover_reg_top/5.kmac_tl_errors.2868679549 May 21 01:56:19 PM PDT 24 May 21 01:56:23 PM PDT 24 1209741813 ps
T85 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.115653072 May 21 01:56:14 PM PDT 24 May 21 01:56:17 PM PDT 24 51130664 ps
T1081 /workspace/coverage/cover_reg_top/6.kmac_tl_errors.3847635335 May 21 01:56:12 PM PDT 24 May 21 01:56:17 PM PDT 24 107502619 ps
T1082 /workspace/coverage/cover_reg_top/8.kmac_intr_test.178651849 May 21 01:56:19 PM PDT 24 May 21 01:56:21 PM PDT 24 14867885 ps
T1083 /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.108769642 May 21 01:56:12 PM PDT 24 May 21 01:56:15 PM PDT 24 64749285 ps
T1084 /workspace/coverage/cover_reg_top/31.kmac_intr_test.3872057872 May 21 01:56:38 PM PDT 24 May 21 01:56:41 PM PDT 24 13678687 ps
T136 /workspace/coverage/cover_reg_top/0.kmac_csr_rw.2363326344 May 21 01:55:55 PM PDT 24 May 21 01:55:57 PM PDT 24 42232168 ps
T159 /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.2713357233 May 21 01:56:29 PM PDT 24 May 21 01:56:34 PM PDT 24 190295447 ps
T88 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2706288399 May 21 01:56:29 PM PDT 24 May 21 01:56:32 PM PDT 24 133746037 ps
T124 /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.1573156557 May 21 01:56:07 PM PDT 24 May 21 01:56:09 PM PDT 24 16033580 ps
T1085 /workspace/coverage/cover_reg_top/43.kmac_intr_test.2738808165 May 21 01:56:43 PM PDT 24 May 21 01:56:46 PM PDT 24 13138981 ps
T1086 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.122151985 May 21 01:56:35 PM PDT 24 May 21 01:56:39 PM PDT 24 140773400 ps
T1087 /workspace/coverage/cover_reg_top/41.kmac_intr_test.2325400868 May 21 01:56:42 PM PDT 24 May 21 01:56:46 PM PDT 24 29625389 ps
T1088 /workspace/coverage/cover_reg_top/1.kmac_csr_rw.3987686564 May 21 01:56:02 PM PDT 24 May 21 01:56:04 PM PDT 24 16083767 ps
T87 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.1467637770 May 21 01:56:13 PM PDT 24 May 21 01:56:15 PM PDT 24 47491192 ps
T1089 /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.2081721209 May 21 01:56:01 PM PDT 24 May 21 01:56:22 PM PDT 24 1245351558 ps
T158 /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.3970410307 May 21 01:56:33 PM PDT 24 May 21 01:56:38 PM PDT 24 478195963 ps
T1090 /workspace/coverage/cover_reg_top/12.kmac_csr_rw.2783864795 May 21 01:56:29 PM PDT 24 May 21 01:56:32 PM PDT 24 431133402 ps
T160 /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.994882994 May 21 01:56:12 PM PDT 24 May 21 01:56:17 PM PDT 24 193000264 ps
T1091 /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.1528201285 May 21 01:56:03 PM PDT 24 May 21 01:56:05 PM PDT 24 54015151 ps
T1092 /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.3508862055 May 21 01:55:56 PM PDT 24 May 21 01:55:58 PM PDT 24 88246187 ps
T162 /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.1321067214 May 21 01:56:08 PM PDT 24 May 21 01:56:12 PM PDT 24 127528695 ps
T1093 /workspace/coverage/cover_reg_top/14.kmac_csr_rw.826183225 May 21 01:56:30 PM PDT 24 May 21 01:56:33 PM PDT 24 20713893 ps
T1094 /workspace/coverage/cover_reg_top/0.kmac_tl_errors.2265526474 May 21 01:55:56 PM PDT 24 May 21 01:55:59 PM PDT 24 102848608 ps
T1095 /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2148512151 May 21 01:56:34 PM PDT 24 May 21 01:56:38 PM PDT 24 249168370 ps
T1096 /workspace/coverage/cover_reg_top/5.kmac_intr_test.1223788847 May 21 01:56:19 PM PDT 24 May 21 01:56:21 PM PDT 24 25210092 ps
T1097 /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.1954402370 May 21 01:56:00 PM PDT 24 May 21 01:56:11 PM PDT 24 486164463 ps
T1098 /workspace/coverage/cover_reg_top/5.kmac_csr_rw.3977324107 May 21 01:56:19 PM PDT 24 May 21 01:56:21 PM PDT 24 58377234 ps
T1099 /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.1671897811 May 21 01:56:17 PM PDT 24 May 21 01:56:21 PM PDT 24 232540964 ps
T90 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.3067456616 May 21 01:55:48 PM PDT 24 May 21 01:55:55 PM PDT 24 259268730 ps
T1100 /workspace/coverage/cover_reg_top/1.kmac_mem_walk.882299358 May 21 01:55:58 PM PDT 24 May 21 01:55:59 PM PDT 24 24342992 ps
T1101 /workspace/coverage/cover_reg_top/13.kmac_tl_errors.517980023 May 21 01:56:30 PM PDT 24 May 21 01:56:33 PM PDT 24 46623731 ps
T1102 /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.3942609055 May 21 01:56:33 PM PDT 24 May 21 01:56:36 PM PDT 24 242984899 ps
T163 /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.3494916871 May 21 01:56:35 PM PDT 24 May 21 01:56:39 PM PDT 24 714753804 ps
T1103 /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.574920151 May 21 01:56:15 PM PDT 24 May 21 01:56:18 PM PDT 24 251013723 ps
T89 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.3430011701 May 21 01:56:34 PM PDT 24 May 21 01:56:38 PM PDT 24 159317619 ps
T1104 /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.4149723903 May 21 01:56:16 PM PDT 24 May 21 01:56:19 PM PDT 24 83723456 ps
T1105 /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.188058367 May 21 01:56:05 PM PDT 24 May 21 01:56:07 PM PDT 24 18039627 ps
T1106 /workspace/coverage/cover_reg_top/7.kmac_csr_rw.866998411 May 21 01:56:12 PM PDT 24 May 21 01:56:15 PM PDT 24 24753520 ps
T1107 /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.418948675 May 21 01:56:08 PM PDT 24 May 21 01:56:19 PM PDT 24 998299431 ps
T1108 /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.2706162065 May 21 01:56:28 PM PDT 24 May 21 01:56:30 PM PDT 24 110274104 ps
T165 /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.2208398595 May 21 01:56:35 PM PDT 24 May 21 01:56:39 PM PDT 24 390873650 ps
T1109 /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.4278580827 May 21 01:56:15 PM PDT 24 May 21 01:56:19 PM PDT 24 174777484 ps
T1110 /workspace/coverage/cover_reg_top/46.kmac_intr_test.2615631949 May 21 01:56:40 PM PDT 24 May 21 01:56:44 PM PDT 24 12772932 ps
T1111 /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.2200620202 May 21 01:56:07 PM PDT 24 May 21 01:56:10 PM PDT 24 270295189 ps
T1112 /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.2650989180 May 21 01:56:07 PM PDT 24 May 21 01:56:10 PM PDT 24 57109118 ps
T1113 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.3789176397 May 21 01:55:59 PM PDT 24 May 21 01:56:01 PM PDT 24 96726218 ps
T1114 /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.2317980297 May 21 01:56:15 PM PDT 24 May 21 01:56:20 PM PDT 24 158937970 ps
T1115 /workspace/coverage/cover_reg_top/10.kmac_intr_test.3915776307 May 21 01:56:21 PM PDT 24 May 21 01:56:23 PM PDT 24 55038823 ps
T1116 /workspace/coverage/cover_reg_top/24.kmac_intr_test.3970123866 May 21 01:56:37 PM PDT 24 May 21 01:56:40 PM PDT 24 23801688 ps
T1117 /workspace/coverage/cover_reg_top/2.kmac_csr_rw.3053813309 May 21 01:56:09 PM PDT 24 May 21 01:56:11 PM PDT 24 21779360 ps
T1118 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.2665975755 May 21 01:55:48 PM PDT 24 May 21 01:55:54 PM PDT 24 39017412 ps
T1119 /workspace/coverage/cover_reg_top/38.kmac_intr_test.1610472858 May 21 01:56:42 PM PDT 24 May 21 01:56:46 PM PDT 24 22407564 ps
T125 /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.2866929782 May 21 01:56:01 PM PDT 24 May 21 01:56:03 PM PDT 24 63613206 ps
T1120 /workspace/coverage/cover_reg_top/48.kmac_intr_test.488916392 May 21 01:56:44 PM PDT 24 May 21 01:56:47 PM PDT 24 13144452 ps
T1121 /workspace/coverage/cover_reg_top/14.kmac_intr_test.3682412918 May 21 01:56:30 PM PDT 24 May 21 01:56:33 PM PDT 24 58829248 ps
T1122 /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.1507925650 May 21 01:56:38 PM PDT 24 May 21 01:56:43 PM PDT 24 70926795 ps
T1123 /workspace/coverage/cover_reg_top/10.kmac_tl_errors.1740982870 May 21 01:56:21 PM PDT 24 May 21 01:56:25 PM PDT 24 125834458 ps
T1124 /workspace/coverage/cover_reg_top/14.kmac_tl_errors.2308288681 May 21 01:56:29 PM PDT 24 May 21 01:56:34 PM PDT 24 114005804 ps
T126 /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.311608505 May 21 01:56:03 PM PDT 24 May 21 01:56:05 PM PDT 24 18442630 ps
T1125 /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.618900604 May 21 01:56:13 PM PDT 24 May 21 01:56:16 PM PDT 24 23683271 ps
T1126 /workspace/coverage/cover_reg_top/3.kmac_intr_test.321693601 May 21 01:56:02 PM PDT 24 May 21 01:56:04 PM PDT 24 51832695 ps
T1127 /workspace/coverage/cover_reg_top/3.kmac_mem_walk.2741629382 May 21 01:56:09 PM PDT 24 May 21 01:56:11 PM PDT 24 45421923 ps
T1128 /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.2258103338 May 21 01:55:59 PM PDT 24 May 21 01:56:01 PM PDT 24 44949575 ps
T1129 /workspace/coverage/cover_reg_top/7.kmac_intr_test.349499693 May 21 01:56:19 PM PDT 24 May 21 01:56:21 PM PDT 24 109422001 ps
T1130 /workspace/coverage/cover_reg_top/19.kmac_csr_rw.3521249047 May 21 01:56:36 PM PDT 24 May 21 01:56:39 PM PDT 24 55359541 ps
T1131 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.2233115160 May 21 01:56:27 PM PDT 24 May 21 01:56:31 PM PDT 24 528382940 ps
T1132 /workspace/coverage/cover_reg_top/0.kmac_mem_walk.702541525 May 21 01:55:55 PM PDT 24 May 21 01:55:57 PM PDT 24 62660056 ps
T1133 /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.3415341654 May 21 01:56:01 PM PDT 24 May 21 01:56:04 PM PDT 24 71997852 ps
T1134 /workspace/coverage/cover_reg_top/34.kmac_intr_test.1830824974 May 21 01:56:37 PM PDT 24 May 21 01:56:40 PM PDT 24 18036951 ps
T1135 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.602923140 May 21 01:56:23 PM PDT 24 May 21 01:56:26 PM PDT 24 114181862 ps
T1136 /workspace/coverage/cover_reg_top/21.kmac_intr_test.261086959 May 21 01:56:36 PM PDT 24 May 21 01:56:39 PM PDT 24 15194328 ps
T1137 /workspace/coverage/cover_reg_top/9.kmac_csr_rw.3096164312 May 21 01:56:17 PM PDT 24 May 21 01:56:20 PM PDT 24 58750376 ps
T1138 /workspace/coverage/cover_reg_top/45.kmac_intr_test.3586355208 May 21 01:56:43 PM PDT 24 May 21 01:56:47 PM PDT 24 18218730 ps
T1139 /workspace/coverage/cover_reg_top/47.kmac_intr_test.2815781125 May 21 01:56:42 PM PDT 24 May 21 01:56:46 PM PDT 24 54626419 ps
T116 /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.3100016359 May 21 01:55:55 PM PDT 24 May 21 01:56:02 PM PDT 24 958156211 ps
T1140 /workspace/coverage/cover_reg_top/36.kmac_intr_test.2381026717 May 21 01:56:40 PM PDT 24 May 21 01:56:43 PM PDT 24 11431882 ps
T1141 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.4143634301 May 21 01:56:16 PM PDT 24 May 21 01:56:19 PM PDT 24 115366801 ps
T1142 /workspace/coverage/cover_reg_top/2.kmac_intr_test.3751724731 May 21 01:56:03 PM PDT 24 May 21 01:56:04 PM PDT 24 21815574 ps
T1143 /workspace/coverage/cover_reg_top/44.kmac_intr_test.1735077330 May 21 01:56:41 PM PDT 24 May 21 01:56:45 PM PDT 24 19203096 ps
T1144 /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.1255821623 May 21 01:56:29 PM PDT 24 May 21 01:56:33 PM PDT 24 25486050 ps
T1145 /workspace/coverage/cover_reg_top/26.kmac_intr_test.1917330088 May 21 01:56:41 PM PDT 24 May 21 01:56:45 PM PDT 24 12746084 ps
T1146 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.406860841 May 21 01:56:36 PM PDT 24 May 21 01:56:39 PM PDT 24 34740177 ps
T1147 /workspace/coverage/cover_reg_top/37.kmac_intr_test.2311852350 May 21 01:56:40 PM PDT 24 May 21 01:56:44 PM PDT 24 27969716 ps
T1148 /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.1626794780 May 21 01:56:34 PM PDT 24 May 21 01:56:38 PM PDT 24 124210079 ps
T1149 /workspace/coverage/cover_reg_top/18.kmac_tl_errors.3731107313 May 21 01:56:35 PM PDT 24 May 21 01:56:39 PM PDT 24 124802823 ps
T1150 /workspace/coverage/cover_reg_top/11.kmac_csr_rw.4024505985 May 21 01:56:21 PM PDT 24 May 21 01:56:24 PM PDT 24 78407374 ps
T1151 /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.759252361 May 21 01:56:15 PM PDT 24 May 21 01:56:18 PM PDT 24 44929731 ps
T1152 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2994595770 May 21 01:56:13 PM PDT 24 May 21 01:56:16 PM PDT 24 425372154 ps
T1153 /workspace/coverage/cover_reg_top/8.kmac_csr_rw.2189029634 May 21 01:56:12 PM PDT 24 May 21 01:56:14 PM PDT 24 37516468 ps
T1154 /workspace/coverage/cover_reg_top/39.kmac_intr_test.3906253959 May 21 01:56:50 PM PDT 24 May 21 01:56:52 PM PDT 24 16255920 ps
T1155 /workspace/coverage/cover_reg_top/9.kmac_intr_test.206063211 May 21 01:56:19 PM PDT 24 May 21 01:56:21 PM PDT 24 22538401 ps
T1156 /workspace/coverage/cover_reg_top/6.kmac_intr_test.4240737313 May 21 01:56:13 PM PDT 24 May 21 01:56:15 PM PDT 24 20986291 ps
T1157 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.2090962588 May 21 01:56:31 PM PDT 24 May 21 01:56:34 PM PDT 24 65070291 ps
T1158 /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.3990800590 May 21 01:55:56 PM PDT 24 May 21 01:55:59 PM PDT 24 35842832 ps
T1159 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.4187341648 May 21 01:55:56 PM PDT 24 May 21 01:55:59 PM PDT 24 705842632 ps
T1160 /workspace/coverage/cover_reg_top/35.kmac_intr_test.1911556175 May 21 01:56:50 PM PDT 24 May 21 01:56:52 PM PDT 24 219336628 ps
T1161 /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.1910974024 May 21 01:55:55 PM PDT 24 May 21 01:55:58 PM PDT 24 51212442 ps
T1162 /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.3324827765 May 21 01:56:07 PM PDT 24 May 21 01:56:10 PM PDT 24 34533064 ps
T1163 /workspace/coverage/cover_reg_top/17.kmac_csr_rw.1416166362 May 21 01:56:31 PM PDT 24 May 21 01:56:34 PM PDT 24 28474808 ps
T1164 /workspace/coverage/cover_reg_top/25.kmac_intr_test.2440725393 May 21 01:56:38 PM PDT 24 May 21 01:56:41 PM PDT 24 22463761 ps
T1165 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.138340751 May 21 01:56:38 PM PDT 24 May 21 01:56:41 PM PDT 24 109308377 ps
T1166 /workspace/coverage/cover_reg_top/42.kmac_intr_test.122907498 May 21 01:56:40 PM PDT 24 May 21 01:56:42 PM PDT 24 12335686 ps
T1167 /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.43846950 May 21 01:56:33 PM PDT 24 May 21 01:56:36 PM PDT 24 733840984 ps
T1168 /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2570487455 May 21 01:56:29 PM PDT 24 May 21 01:56:33 PM PDT 24 39906711 ps
T1169 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.4029935392 May 21 01:56:27 PM PDT 24 May 21 01:56:30 PM PDT 24 487276994 ps
T1170 /workspace/coverage/cover_reg_top/16.kmac_intr_test.3308933542 May 21 01:56:33 PM PDT 24 May 21 01:56:35 PM PDT 24 40892845 ps
T1171 /workspace/coverage/cover_reg_top/13.kmac_intr_test.1199056727 May 21 01:56:29 PM PDT 24 May 21 01:56:32 PM PDT 24 29929016 ps
T1172 /workspace/coverage/cover_reg_top/4.kmac_intr_test.2680340907 May 21 01:56:08 PM PDT 24 May 21 01:56:09 PM PDT 24 14691637 ps
T1173 /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.2274690568 May 21 01:56:29 PM PDT 24 May 21 01:56:34 PM PDT 24 758577528 ps
T1174 /workspace/coverage/cover_reg_top/2.kmac_mem_walk.3948563561 May 21 01:55:59 PM PDT 24 May 21 01:56:01 PM PDT 24 83087561 ps
T1175 /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.584757369 May 21 01:56:10 PM PDT 24 May 21 01:56:20 PM PDT 24 1402004190 ps
T1176 /workspace/coverage/cover_reg_top/15.kmac_tl_errors.4223476842 May 21 01:56:29 PM PDT 24 May 21 01:56:33 PM PDT 24 105221193 ps
T1177 /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.1068981970 May 21 01:56:29 PM PDT 24 May 21 01:56:33 PM PDT 24 26258562 ps
T1178 /workspace/coverage/cover_reg_top/49.kmac_intr_test.2384787939 May 21 01:56:40 PM PDT 24 May 21 01:56:43 PM PDT 24 21660159 ps
T1179 /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.949888485 May 21 01:56:12 PM PDT 24 May 21 01:56:16 PM PDT 24 184197651 ps
T1180 /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.300999463 May 21 01:56:23 PM PDT 24 May 21 01:56:27 PM PDT 24 560589856 ps
T1181 /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.202740176 May 21 01:56:00 PM PDT 24 May 21 01:56:05 PM PDT 24 293018633 ps
T164 /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.2028284721 May 21 01:56:35 PM PDT 24 May 21 01:56:42 PM PDT 24 330498807 ps
T1182 /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.2297929571 May 21 01:56:03 PM PDT 24 May 21 01:56:04 PM PDT 24 89270790 ps
T1183 /workspace/coverage/cover_reg_top/19.kmac_intr_test.4246773130 May 21 01:56:36 PM PDT 24 May 21 01:56:38 PM PDT 24 29128669 ps
T1184 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.498500427 May 21 01:56:13 PM PDT 24 May 21 01:56:17 PM PDT 24 96346755 ps
T1185 /workspace/coverage/cover_reg_top/29.kmac_intr_test.4268990307 May 21 01:56:40 PM PDT 24 May 21 01:56:44 PM PDT 24 29081692 ps
T1186 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.880691401 May 21 01:56:09 PM PDT 24 May 21 01:56:11 PM PDT 24 91253991 ps
T1187 /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3587658313 May 21 01:56:27 PM PDT 24 May 21 01:56:30 PM PDT 24 74231754 ps
T1188 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.1063190881 May 21 01:56:36 PM PDT 24 May 21 01:56:40 PM PDT 24 94918072 ps
T1189 /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1360602002 May 21 01:56:28 PM PDT 24 May 21 01:56:32 PM PDT 24 208569215 ps
T1190 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.4236538268 May 21 01:55:57 PM PDT 24 May 21 01:56:01 PM PDT 24 746378678 ps
T1191 /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.206945933 May 21 01:56:32 PM PDT 24 May 21 01:56:36 PM PDT 24 456802792 ps
T1192 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.2498859395 May 21 01:56:08 PM PDT 24 May 21 01:56:12 PM PDT 24 925810472 ps
T1193 /workspace/coverage/cover_reg_top/12.kmac_intr_test.706450912 May 21 01:56:28 PM PDT 24 May 21 01:56:30 PM PDT 24 38878319 ps
T1194 /workspace/coverage/cover_reg_top/12.kmac_tl_errors.2625547251 May 21 01:56:29 PM PDT 24 May 21 01:56:34 PM PDT 24 160188638 ps
T1195 /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.1023640494 May 21 01:56:09 PM PDT 24 May 21 01:56:18 PM PDT 24 159553337 ps
T1196 /workspace/coverage/cover_reg_top/32.kmac_intr_test.504515664 May 21 01:56:39 PM PDT 24 May 21 01:56:42 PM PDT 24 36395759 ps
T1197 /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.1052290558 May 21 01:56:09 PM PDT 24 May 21 01:56:12 PM PDT 24 94164392 ps
T1198 /workspace/coverage/cover_reg_top/30.kmac_intr_test.2763310944 May 21 01:56:41 PM PDT 24 May 21 01:56:45 PM PDT 24 57906916 ps
T1199 /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.3039599079 May 21 01:56:36 PM PDT 24 May 21 01:56:41 PM PDT 24 281023519 ps
T127 /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.2283768868 May 21 01:55:55 PM PDT 24 May 21 01:55:57 PM PDT 24 152150471 ps
T1200 /workspace/coverage/cover_reg_top/3.kmac_tl_errors.845938539 May 21 01:56:01 PM PDT 24 May 21 01:56:04 PM PDT 24 183910593 ps
T1201 /workspace/coverage/cover_reg_top/8.kmac_tl_errors.1097805643 May 21 01:56:13 PM PDT 24 May 21 01:56:17 PM PDT 24 66318858 ps
T1202 /workspace/coverage/cover_reg_top/11.kmac_tl_errors.822935791 May 21 01:56:22 PM PDT 24 May 21 01:56:27 PM PDT 24 52146625 ps
T1203 /workspace/coverage/cover_reg_top/3.kmac_csr_rw.3170613486 May 21 01:56:02 PM PDT 24 May 21 01:56:04 PM PDT 24 22849359 ps
T1204 /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2224058981 May 21 01:56:11 PM PDT 24 May 21 01:56:14 PM PDT 24 166019062 ps
T1205 /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.1000631035 May 21 01:55:54 PM PDT 24 May 21 01:56:06 PM PDT 24 4817529483 ps
T1206 /workspace/coverage/cover_reg_top/0.kmac_intr_test.852535030 May 21 01:55:55 PM PDT 24 May 21 01:55:57 PM PDT 24 15850168 ps
T1207 /workspace/coverage/cover_reg_top/10.kmac_csr_rw.3163105843 May 21 01:56:21 PM PDT 24 May 21 01:56:23 PM PDT 24 19743207 ps
T1208 /workspace/coverage/cover_reg_top/1.kmac_tl_errors.3713267941 May 21 01:55:55 PM PDT 24 May 21 01:55:59 PM PDT 24 75218655 ps
T1209 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3120864775 May 21 01:56:28 PM PDT 24 May 21 01:56:30 PM PDT 24 61779699 ps
T1210 /workspace/coverage/cover_reg_top/4.kmac_csr_rw.4044317048 May 21 01:56:05 PM PDT 24 May 21 01:56:07 PM PDT 24 29893696 ps
T1211 /workspace/coverage/cover_reg_top/28.kmac_intr_test.3105510681 May 21 01:56:41 PM PDT 24 May 21 01:56:45 PM PDT 24 13429586 ps
T161 /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.3011986625 May 21 01:56:28 PM PDT 24 May 21 01:56:35 PM PDT 24 950275320 ps
T1212 /workspace/coverage/cover_reg_top/2.kmac_tl_errors.4265505996 May 21 01:56:01 PM PDT 24 May 21 01:56:03 PM PDT 24 36951922 ps
T1213 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.384777390 May 21 01:56:30 PM PDT 24 May 21 01:56:34 PM PDT 24 122718866 ps
T1214 /workspace/coverage/cover_reg_top/20.kmac_intr_test.3491580838 May 21 01:56:35 PM PDT 24 May 21 01:56:38 PM PDT 24 51691233 ps
T1215 /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3031581548 May 21 01:56:30 PM PDT 24 May 21 01:56:35 PM PDT 24 106674281 ps
T1216 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.3164389617 May 21 01:56:13 PM PDT 24 May 21 01:56:15 PM PDT 24 30539699 ps
T1217 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.2809825397 May 21 01:56:09 PM PDT 24 May 21 01:56:11 PM PDT 24 123962251 ps
T1218 /workspace/coverage/cover_reg_top/17.kmac_tl_errors.2311764061 May 21 01:56:28 PM PDT 24 May 21 01:56:31 PM PDT 24 71560672 ps
T1219 /workspace/coverage/cover_reg_top/4.kmac_mem_walk.2467243509 May 21 01:56:05 PM PDT 24 May 21 01:56:07 PM PDT 24 148863690 ps
T1220 /workspace/coverage/cover_reg_top/27.kmac_intr_test.2259995944 May 21 01:56:33 PM PDT 24 May 21 01:56:36 PM PDT 24 44056690 ps
T1221 /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.1638134273 May 21 01:56:01 PM PDT 24 May 21 01:56:04 PM PDT 24 121288766 ps
T1222 /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.2339280288 May 21 01:56:22 PM PDT 24 May 21 01:56:27 PM PDT 24 475557991 ps
T128 /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.2558544412 May 21 01:55:52 PM PDT 24 May 21 01:55:55 PM PDT 24 246003706 ps
T1223 /workspace/coverage/cover_reg_top/19.kmac_tl_errors.3379019602 May 21 01:56:36 PM PDT 24 May 21 01:56:40 PM PDT 24 111778713 ps
T1224 /workspace/coverage/cover_reg_top/11.kmac_intr_test.3807855383 May 21 01:56:21 PM PDT 24 May 21 01:56:24 PM PDT 24 34775281 ps
T1225 /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.3302469115 May 21 01:55:59 PM PDT 24 May 21 01:56:03 PM PDT 24 242399613 ps
T1226 /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.2798678213 May 21 01:56:22 PM PDT 24 May 21 01:56:27 PM PDT 24 189799544 ps
T166 /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.2434796591 May 21 01:56:36 PM PDT 24 May 21 01:56:44 PM PDT 24 2585176703 ps
T1227 /workspace/coverage/cover_reg_top/15.kmac_intr_test.1094731013 May 21 01:56:33 PM PDT 24 May 21 01:56:35 PM PDT 24 39919747 ps
T1228 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.2948554236 May 21 01:56:13 PM PDT 24 May 21 01:56:16 PM PDT 24 128885312 ps
T1229 /workspace/coverage/cover_reg_top/16.kmac_csr_rw.1381964906 May 21 01:56:30 PM PDT 24 May 21 01:56:33 PM PDT 24 51201726 ps
T1230 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.3727421988 May 21 01:56:22 PM PDT 24 May 21 01:56:25 PM PDT 24 134818697 ps
T1231 /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.4261836114 May 21 01:56:09 PM PDT 24 May 21 01:56:12 PM PDT 24 112968347 ps
T1232 /workspace/coverage/cover_reg_top/7.kmac_tl_errors.814221079 May 21 01:56:16 PM PDT 24 May 21 01:56:20 PM PDT 24 22707772 ps
T1233 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.2635303124 May 21 01:56:22 PM PDT 24 May 21 01:56:25 PM PDT 24 159780082 ps
T1234 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.3409689581 May 21 01:56:11 PM PDT 24 May 21 01:56:14 PM PDT 24 213676776 ps
T1235 /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.3466545328 May 21 01:56:13 PM PDT 24 May 21 01:56:16 PM PDT 24 56172199 ps

Test location /workspace/coverage/default/22.kmac_stress_all.2284985521
Short name T7
Test name
Test status
Simulation time 82729275292 ps
CPU time 677.13 seconds
Started May 21 12:54:48 PM PDT 24
Finished May 21 01:06:07 PM PDT 24
Peak memory 271688 kb
Host smart-475885b4-ba46-4eea-8a78-f141b95b91b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2284985521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.2284985521 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_stress_all/latest

Test location /workspace/coverage/default/46.kmac_stress_all_with_rand_reset.4256916540
Short name T9
Test name
Test status
Simulation time 245197362439 ps
CPU time 1255.68 seconds
Started May 21 12:59:56 PM PDT 24
Finished May 21 01:20:53 PM PDT 24
Peak memory 287596 kb
Host smart-d8343ac1-3539-4c0f-a08c-b2897ed8b897
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4256916540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all_with_rand_reset.4256916540 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.4229023457
Short name T110
Test name
Test status
Simulation time 177071769 ps
CPU time 3.06 seconds
Started May 21 01:55:58 PM PDT 24
Finished May 21 01:56:02 PM PDT 24
Peak memory 216720 kb
Host smart-85f393d8-7fdb-45a1-85c6-a01ed06c573f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229023457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.42290
23457 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/1.kmac_sec_cm.4285410980
Short name T28
Test name
Test status
Simulation time 2387195716 ps
CPU time 45.95 seconds
Started May 21 12:53:22 PM PDT 24
Finished May 21 12:54:13 PM PDT 24
Peak memory 256676 kb
Host smart-ffeb0d4c-0b8d-4b06-a30d-fbec4e2976d4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285410980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.4285410980 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/1.kmac_sec_cm/latest

Test location /workspace/coverage/default/20.kmac_key_error.3487214000
Short name T6
Test name
Test status
Simulation time 1641178620 ps
CPU time 13.51 seconds
Started May 21 12:54:29 PM PDT 24
Finished May 21 12:54:45 PM PDT 24
Peak memory 218568 kb
Host smart-b54a83b4-060d-4d55-ae02-066400a5f761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487214000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.3487214000 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_key_error/latest

Test location /workspace/coverage/default/5.kmac_lc_escalation.2164340489
Short name T14
Test name
Test status
Simulation time 44768113 ps
CPU time 1.33 seconds
Started May 21 12:53:36 PM PDT 24
Finished May 21 12:53:40 PM PDT 24
Peak memory 218580 kb
Host smart-e40996dd-a821-412d-a2ce-e1026d884717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164340489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.2164340489 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/5.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.1467637770
Short name T87
Test name
Test status
Simulation time 47491192 ps
CPU time 1.39 seconds
Started May 21 01:56:13 PM PDT 24
Finished May 21 01:56:15 PM PDT 24
Peak memory 218008 kb
Host smart-441b183a-1425-4bf3-9fd1-431a13d6435c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467637770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_
errors.1467637770 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/default/18.kmac_error.1035315145
Short name T148
Test name
Test status
Simulation time 4793196267 ps
CPU time 351.65 seconds
Started May 21 12:54:15 PM PDT 24
Finished May 21 01:00:11 PM PDT 24
Peak memory 259540 kb
Host smart-1d828f3e-41dd-4ca0-9ac4-05408710e562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035315145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.1035315145 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_error/latest

Test location /workspace/coverage/default/26.kmac_lc_escalation.681370924
Short name T13
Test name
Test status
Simulation time 51485597 ps
CPU time 1.56 seconds
Started May 21 12:55:04 PM PDT 24
Finished May 21 12:55:07 PM PDT 24
Peak memory 218668 kb
Host smart-aa29d023-de18-41ef-aa8c-955c808c4052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681370924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.681370924 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/26.kmac_lc_escalation/latest

Test location /workspace/coverage/default/8.kmac_entropy_ready_error.839816463
Short name T10
Test name
Test status
Simulation time 19293815140 ps
CPU time 23.81 seconds
Started May 21 12:54:10 PM PDT 24
Finished May 21 12:54:37 PM PDT 24
Peak memory 226736 kb
Host smart-7964ba60-bb8e-4c20-b97e-a832e401a0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839816463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.839816463 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_ready_error/latest

Test location /workspace/coverage/cover_reg_top/23.kmac_intr_test.2142151021
Short name T149
Test name
Test status
Simulation time 41904681 ps
CPU time 0.83 seconds
Started May 21 01:56:36 PM PDT 24
Finished May 21 01:56:40 PM PDT 24
Peak memory 216420 kb
Host smart-fe1ddc6f-e4f5-4fee-8eae-44f297a0256f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142151021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.2142151021 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_intr_test/latest

Test location /workspace/coverage/default/6.kmac_edn_timeout_error.3397454942
Short name T68
Test name
Test status
Simulation time 14707247 ps
CPU time 0.87 seconds
Started May 21 12:53:51 PM PDT 24
Finished May 21 12:53:55 PM PDT 24
Peak memory 218280 kb
Host smart-c1252b0c-dadd-4703-8cd8-f963f1c21db0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3397454942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.3397454942 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/32.kmac_stress_all.321573868
Short name T57
Test name
Test status
Simulation time 253127717936 ps
CPU time 1517.44 seconds
Started May 21 12:56:01 PM PDT 24
Finished May 21 01:21:19 PM PDT 24
Peak memory 381596 kb
Host smart-fb480a4f-c196-433b-8d53-508facf3641b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=321573868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.321573868 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_stress_all/latest

Test location /workspace/coverage/default/30.kmac_lc_escalation.1909258387
Short name T43
Test name
Test status
Simulation time 116109316 ps
CPU time 5.2 seconds
Started May 21 12:55:37 PM PDT 24
Finished May 21 12:55:44 PM PDT 24
Peak memory 226772 kb
Host smart-c7df41df-c122-4eaa-a6b8-0496d12f7899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909258387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.1909258387 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/30.kmac_lc_escalation/latest

Test location /workspace/coverage/default/0.kmac_entropy_mode_error.1930298609
Short name T275
Test name
Test status
Simulation time 37540687 ps
CPU time 0.9 seconds
Started May 21 12:53:11 PM PDT 24
Finished May 21 12:53:20 PM PDT 24
Peak memory 220516 kb
Host smart-e01b1056-4bef-43f7-ad63-45fd245b51f1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1930298609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.1930298609 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/10.kmac_lc_escalation.3984189685
Short name T268
Test name
Test status
Simulation time 33588360 ps
CPU time 1.44 seconds
Started May 21 12:53:58 PM PDT 24
Finished May 21 12:54:02 PM PDT 24
Peak memory 218896 kb
Host smart-37382717-7a96-46dd-8714-f3cf6c5fd7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984189685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.3984189685 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/10.kmac_lc_escalation/latest

Test location /workspace/coverage/default/29.kmac_lc_escalation.2128293503
Short name T77
Test name
Test status
Simulation time 110005646 ps
CPU time 1.39 seconds
Started May 21 12:55:31 PM PDT 24
Finished May 21 12:55:33 PM PDT 24
Peak memory 219624 kb
Host smart-33d73f5b-d2ce-47f3-9a48-6b788e772f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128293503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.2128293503 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/29.kmac_lc_escalation/latest

Test location /workspace/coverage/default/21.kmac_stress_all.3895699143
Short name T41
Test name
Test status
Simulation time 44116565477 ps
CPU time 1131.76 seconds
Started May 21 12:54:41 PM PDT 24
Finished May 21 01:13:34 PM PDT 24
Peak memory 316892 kb
Host smart-5ddd252d-d98a-4702-9c25-1ce016eaeb5d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3895699143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.3895699143 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.1329541809
Short name T111
Test name
Test status
Simulation time 190298807 ps
CPU time 4.75 seconds
Started May 21 01:56:19 PM PDT 24
Finished May 21 01:56:25 PM PDT 24
Peak memory 216756 kb
Host smart-47ff7024-beb6-4bd0-935e-146c814b5073
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329541809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.13295
41809 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.2283768868
Short name T127
Test name
Test status
Simulation time 152150471 ps
CPU time 1.34 seconds
Started May 21 01:55:55 PM PDT 24
Finished May 21 01:55:57 PM PDT 24
Peak memory 216660 kb
Host smart-5140d417-c932-4433-9190-d2b8a201c082
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283768868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia
l_access.2283768868 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mem_partial_access/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_shake_128.817042366
Short name T169
Test name
Test status
Simulation time 722259820419 ps
CPU time 5713.5 seconds
Started May 21 12:54:05 PM PDT 24
Finished May 21 02:29:23 PM PDT 24
Peak memory 632260 kb
Host smart-126bd60c-fdbc-49e3-8246-b715258bb644
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=817042366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_128.817042366 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/0.kmac_lc_escalation.2926344646
Short name T52
Test name
Test status
Simulation time 42344865 ps
CPU time 1.48 seconds
Started May 21 12:53:16 PM PDT 24
Finished May 21 12:53:24 PM PDT 24
Peak memory 219476 kb
Host smart-aedb4a47-e7e0-40ce-b8b9-850d4e9ce82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926344646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.2926344646 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/0.kmac_lc_escalation/latest

Test location /workspace/coverage/default/25.kmac_lc_escalation.1565933252
Short name T67
Test name
Test status
Simulation time 35135294 ps
CPU time 1.34 seconds
Started May 21 12:54:58 PM PDT 24
Finished May 21 12:55:01 PM PDT 24
Peak memory 218684 kb
Host smart-688e5818-efb9-4403-80dc-8618eb96e3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565933252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.1565933252 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/25.kmac_lc_escalation/latest

Test location /workspace/coverage/default/0.kmac_alert_test.3511110151
Short name T349
Test name
Test status
Simulation time 23122742 ps
CPU time 0.8 seconds
Started May 21 12:53:14 PM PDT 24
Finished May 21 12:53:22 PM PDT 24
Peak memory 218544 kb
Host smart-f3344d58-9819-49dc-9ba3-1b9b7ec58b52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511110151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.3511110151 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.2233115160
Short name T1131
Test name
Test status
Simulation time 528382940 ps
CPU time 3.35 seconds
Started May 21 01:56:27 PM PDT 24
Finished May 21 01:56:31 PM PDT 24
Peak memory 219020 kb
Host smart-040195de-c3ea-4b2e-93d8-927f35aa9ea9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233115160 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kma
c_shadow_reg_errors_with_csr_rw.2233115160 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_intr_test.3150533401
Short name T152
Test name
Test status
Simulation time 19132223 ps
CPU time 0.81 seconds
Started May 21 01:55:56 PM PDT 24
Finished May 21 01:55:58 PM PDT 24
Peak memory 216468 kb
Host smart-c8420d0e-2cf9-4ae9-9fb2-3be694ae15b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150533401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.3150533401 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_intr_test/latest

Test location /workspace/coverage/default/5.kmac_error.487424336
Short name T46
Test name
Test status
Simulation time 15510782793 ps
CPU time 243.03 seconds
Started May 21 12:53:51 PM PDT 24
Finished May 21 12:57:58 PM PDT 24
Peak memory 259512 kb
Host smart-99e9a8d3-2b3b-497e-a0ba-ee01558c76c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487424336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.487424336 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_refresh.3326464120
Short name T154
Test name
Test status
Simulation time 17235295345 ps
CPU time 365.21 seconds
Started May 21 12:53:44 PM PDT 24
Finished May 21 12:59:52 PM PDT 24
Peak memory 249164 kb
Host smart-456fd81f-18df-414a-9449-e03135d139c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326464120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.3326464120 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/9.kmac_entropy_refresh/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.1918341351
Short name T112
Test name
Test status
Simulation time 391138823 ps
CPU time 4.7 seconds
Started May 21 01:56:23 PM PDT 24
Finished May 21 01:56:30 PM PDT 24
Peak memory 216708 kb
Host smart-46e18c5c-7eec-477b-bbcd-ee8afabaec98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918341351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.1918
341351 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.3494916871
Short name T163
Test name
Test status
Simulation time 714753804 ps
CPU time 3.01 seconds
Started May 21 01:56:35 PM PDT 24
Finished May 21 01:56:39 PM PDT 24
Peak memory 216700 kb
Host smart-ebbb8109-db36-43f5-8200-d1868eb2b94e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494916871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.3494
916871 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/23.kmac_stress_all_with_rand_reset.3167529403
Short name T59
Test name
Test status
Simulation time 328568493501 ps
CPU time 3146.51 seconds
Started May 21 12:54:55 PM PDT 24
Finished May 21 01:47:24 PM PDT 24
Peak memory 390900 kb
Host smart-2ea6a492-85a5-4cea-93e8-42e1e65a7814
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3167529403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all_with_rand_reset.3167529403 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.kmac_stress_all.3952286090
Short name T20
Test name
Test status
Simulation time 71146005615 ps
CPU time 584.91 seconds
Started May 21 12:53:44 PM PDT 24
Finished May 21 01:03:32 PM PDT 24
Peak memory 308840 kb
Host smart-c0457230-bdca-41b3-bc8b-88db5bf56ac2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3952286090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.3952286090 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.3067456616
Short name T90
Test name
Test status
Simulation time 259268730 ps
CPU time 2.01 seconds
Started May 21 01:55:48 PM PDT 24
Finished May 21 01:55:55 PM PDT 24
Peak memory 219304 kb
Host smart-09f5bf25-3570-4bc7-9c81-f319decc2234
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067456616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac
_shadow_reg_errors_with_csr_rw.3067456616 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.3100016359
Short name T116
Test name
Test status
Simulation time 958156211 ps
CPU time 5.26 seconds
Started May 21 01:55:55 PM PDT 24
Finished May 21 01:56:02 PM PDT 24
Peak memory 216712 kb
Host smart-1bd4ca35-1aac-4c54-b5c9-9a319c6eb6e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100016359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.31000
16359 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/10.kmac_stress_all_with_rand_reset.4179836467
Short name T80
Test name
Test status
Simulation time 243784759638 ps
CPU time 855.61 seconds
Started May 21 12:53:50 PM PDT 24
Finished May 21 01:08:10 PM PDT 24
Peak memory 276172 kb
Host smart-bd505e7a-7437-41f4-a653-a4e30896cb5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4179836467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all_with_rand_reset.4179836467 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.2729256265
Short name T132
Test name
Test status
Simulation time 1921345634 ps
CPU time 10.5 seconds
Started May 21 01:55:55 PM PDT 24
Finished May 21 01:56:07 PM PDT 24
Peak memory 216652 kb
Host smart-5e9a20e1-da52-4976-9cb6-456998900aa4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729256265 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.2729256
265 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.1000631035
Short name T1205
Test name
Test status
Simulation time 4817529483 ps
CPU time 11.25 seconds
Started May 21 01:55:54 PM PDT 24
Finished May 21 01:56:06 PM PDT 24
Peak memory 216816 kb
Host smart-d8b18308-a5b9-4554-ae64-0a1d76dc8365
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000631035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.1000631
035 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.3508862055
Short name T1092
Test name
Test status
Simulation time 88246187 ps
CPU time 0.96 seconds
Started May 21 01:55:56 PM PDT 24
Finished May 21 01:55:58 PM PDT 24
Peak memory 216428 kb
Host smart-054faf20-c119-47b2-b3a0-10cfa9f23658
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508862055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.3508862
055 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.3990800590
Short name T1158
Test name
Test status
Simulation time 35842832 ps
CPU time 2.28 seconds
Started May 21 01:55:56 PM PDT 24
Finished May 21 01:55:59 PM PDT 24
Peak memory 221804 kb
Host smart-80e613ec-838c-45b2-bc25-5b611db62082
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990800590 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.3990800590 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_rw.2363326344
Short name T136
Test name
Test status
Simulation time 42232168 ps
CPU time 0.97 seconds
Started May 21 01:55:55 PM PDT 24
Finished May 21 01:55:57 PM PDT 24
Peak memory 216396 kb
Host smart-3eb8b2aa-8cd1-4e44-bc6e-44a940a01de4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363326344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.2363326344 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_intr_test.852535030
Short name T1206
Test name
Test status
Simulation time 15850168 ps
CPU time 0.79 seconds
Started May 21 01:55:55 PM PDT 24
Finished May 21 01:55:57 PM PDT 24
Peak memory 216312 kb
Host smart-222e2aa2-8f3c-4ef6-b995-5937c9f78251
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852535030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.852535030 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/0.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_walk.702541525
Short name T1132
Test name
Test status
Simulation time 62660056 ps
CPU time 0.78 seconds
Started May 21 01:55:55 PM PDT 24
Finished May 21 01:55:57 PM PDT 24
Peak memory 216404 kb
Host smart-fdb1ed55-9732-41da-8307-5f1e4c8291cd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702541525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.702541525 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.1910974024
Short name T1161
Test name
Test status
Simulation time 51212442 ps
CPU time 1.68 seconds
Started May 21 01:55:55 PM PDT 24
Finished May 21 01:55:58 PM PDT 24
Peak memory 216720 kb
Host smart-2861ef6d-b47f-4b8b-9707-6d6cacdccf18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910974024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr
_outstanding.1910974024 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.2665975755
Short name T1118
Test name
Test status
Simulation time 39017412 ps
CPU time 0.91 seconds
Started May 21 01:55:48 PM PDT 24
Finished May 21 01:55:54 PM PDT 24
Peak memory 216464 kb
Host smart-5b85a70c-575c-48af-8daa-84a309300e0b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665975755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_
errors.2665975755 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_errors.2265526474
Short name T1094
Test name
Test status
Simulation time 102848608 ps
CPU time 1.9 seconds
Started May 21 01:55:56 PM PDT 24
Finished May 21 01:55:59 PM PDT 24
Peak memory 216772 kb
Host smart-200ce6eb-b15a-4dac-9707-e0c7f1035fb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265526474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.2265526474 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.2436165222
Short name T167
Test name
Test status
Simulation time 386429205 ps
CPU time 9.64 seconds
Started May 21 01:55:58 PM PDT 24
Finished May 21 01:56:08 PM PDT 24
Peak memory 216584 kb
Host smart-e48c8e98-74d9-42cf-adf6-b70cce693751
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436165222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.2436165
222 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.4173241810
Short name T1077
Test name
Test status
Simulation time 3356932131 ps
CPU time 21.09 seconds
Started May 21 01:55:55 PM PDT 24
Finished May 21 01:56:17 PM PDT 24
Peak memory 216764 kb
Host smart-e5fde6a2-64d6-46ae-bd4f-3ebb26bef374
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173241810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.4173241
810 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.2297929571
Short name T1182
Test name
Test status
Simulation time 89270790 ps
CPU time 0.98 seconds
Started May 21 01:56:03 PM PDT 24
Finished May 21 01:56:04 PM PDT 24
Peak memory 216380 kb
Host smart-1461c6c5-3875-478c-80b7-f0ddaf5f62c3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297929571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.2297929
571 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.2667743759
Short name T1074
Test name
Test status
Simulation time 1179808115 ps
CPU time 2.81 seconds
Started May 21 01:55:59 PM PDT 24
Finished May 21 01:56:02 PM PDT 24
Peak memory 219904 kb
Host smart-23c1af61-8a4b-43aa-9d11-5f3abc99fe79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667743759 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.2667743759 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_rw.3987686564
Short name T1088
Test name
Test status
Simulation time 16083767 ps
CPU time 0.96 seconds
Started May 21 01:56:02 PM PDT 24
Finished May 21 01:56:04 PM PDT 24
Peak memory 216372 kb
Host smart-f1a411f8-9751-40a7-ac67-0e4a31d371ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987686564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.3987686564 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.2558544412
Short name T128
Test name
Test status
Simulation time 246003706 ps
CPU time 1.28 seconds
Started May 21 01:55:52 PM PDT 24
Finished May 21 01:55:55 PM PDT 24
Peak memory 216720 kb
Host smart-eb97b3a0-d527-4141-8769-5c3c543334ca
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558544412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partia
l_access.2558544412 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_walk.882299358
Short name T1100
Test name
Test status
Simulation time 24342992 ps
CPU time 0.8 seconds
Started May 21 01:55:58 PM PDT 24
Finished May 21 01:55:59 PM PDT 24
Peak memory 216428 kb
Host smart-8006989b-c0bd-4389-b541-cc00d242becb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882299358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.882299358 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.2258103338
Short name T1128
Test name
Test status
Simulation time 44949575 ps
CPU time 1.55 seconds
Started May 21 01:55:59 PM PDT 24
Finished May 21 01:56:01 PM PDT 24
Peak memory 216692 kb
Host smart-659cc529-74e9-43fc-9fe7-668f9ab2b635
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258103338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr
_outstanding.2258103338 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.4187341648
Short name T1159
Test name
Test status
Simulation time 705842632 ps
CPU time 1.62 seconds
Started May 21 01:55:56 PM PDT 24
Finished May 21 01:55:59 PM PDT 24
Peak memory 217188 kb
Host smart-62595dba-de44-4bac-82b0-34c63d3d85f7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187341648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_
errors.4187341648 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_errors.3713267941
Short name T1208
Test name
Test status
Simulation time 75218655 ps
CPU time 2.46 seconds
Started May 21 01:55:55 PM PDT 24
Finished May 21 01:55:59 PM PDT 24
Peak memory 216800 kb
Host smart-f2c22f12-4588-4b57-a206-67ed6da61e78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713267941 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.3713267941 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.300999463
Short name T1180
Test name
Test status
Simulation time 560589856 ps
CPU time 2.69 seconds
Started May 21 01:56:23 PM PDT 24
Finished May 21 01:56:27 PM PDT 24
Peak memory 222196 kb
Host smart-09954bf2-52e6-4e59-96c8-e4209f3c3239
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300999463 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.300999463 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_rw.3163105843
Short name T1207
Test name
Test status
Simulation time 19743207 ps
CPU time 0.99 seconds
Started May 21 01:56:21 PM PDT 24
Finished May 21 01:56:23 PM PDT 24
Peak memory 216484 kb
Host smart-5dc38bbd-7cb2-4c6e-be69-116eccb456b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163105843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.3163105843 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_intr_test.3915776307
Short name T1115
Test name
Test status
Simulation time 55038823 ps
CPU time 0.8 seconds
Started May 21 01:56:21 PM PDT 24
Finished May 21 01:56:23 PM PDT 24
Peak memory 216368 kb
Host smart-a955409b-5a9a-445c-969e-b036776567a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915776307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.3915776307 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.2339280288
Short name T1222
Test name
Test status
Simulation time 475557991 ps
CPU time 2.79 seconds
Started May 21 01:56:22 PM PDT 24
Finished May 21 01:56:27 PM PDT 24
Peak memory 216636 kb
Host smart-73c0af45-0f99-42e9-9ac6-744585879bf3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339280288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_cs
r_outstanding.2339280288 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.3727421988
Short name T1230
Test name
Test status
Simulation time 134818697 ps
CPU time 1.21 seconds
Started May 21 01:56:22 PM PDT 24
Finished May 21 01:56:25 PM PDT 24
Peak memory 217124 kb
Host smart-cff2fb88-5cc7-4ba3-b827-2e4a3258df45
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727421988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg
_errors.3727421988 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_errors.1740982870
Short name T1123
Test name
Test status
Simulation time 125834458 ps
CPU time 2.21 seconds
Started May 21 01:56:21 PM PDT 24
Finished May 21 01:56:25 PM PDT 24
Peak memory 216772 kb
Host smart-eda3e6b1-8b9f-432f-9138-be2fce818c22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740982870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.1740982870 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.4293991581
Short name T135
Test name
Test status
Simulation time 183446577 ps
CPU time 2.82 seconds
Started May 21 01:56:28 PM PDT 24
Finished May 21 01:56:33 PM PDT 24
Peak memory 221704 kb
Host smart-a1aae7dd-5503-4eea-a059-d42e606836c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293991581 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.4293991581 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_rw.4024505985
Short name T1150
Test name
Test status
Simulation time 78407374 ps
CPU time 1.02 seconds
Started May 21 01:56:21 PM PDT 24
Finished May 21 01:56:24 PM PDT 24
Peak memory 216420 kb
Host smart-837c1162-bd5a-41f8-a4a7-cbe21c896e70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024505985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.4024505985 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_intr_test.3807855383
Short name T1224
Test name
Test status
Simulation time 34775281 ps
CPU time 0.8 seconds
Started May 21 01:56:21 PM PDT 24
Finished May 21 01:56:24 PM PDT 24
Peak memory 216352 kb
Host smart-e0df1829-4100-4156-8e8c-261da9e94110
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807855383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.3807855383 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.2706162065
Short name T1108
Test name
Test status
Simulation time 110274104 ps
CPU time 1.79 seconds
Started May 21 01:56:28 PM PDT 24
Finished May 21 01:56:30 PM PDT 24
Peak memory 216716 kb
Host smart-17ae32ff-1cc9-4566-86cd-9871c6e545d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706162065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_cs
r_outstanding.2706162065 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.2635303124
Short name T1233
Test name
Test status
Simulation time 159780082 ps
CPU time 1.31 seconds
Started May 21 01:56:22 PM PDT 24
Finished May 21 01:56:25 PM PDT 24
Peak memory 217136 kb
Host smart-ed151001-94f1-4e8b-b65d-7be592f0074e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635303124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg
_errors.2635303124 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.602923140
Short name T1135
Test name
Test status
Simulation time 114181862 ps
CPU time 1.68 seconds
Started May 21 01:56:23 PM PDT 24
Finished May 21 01:56:26 PM PDT 24
Peak memory 216976 kb
Host smart-588175b8-ccb1-4e40-9249-be0b2a768248
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602923140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac
_shadow_reg_errors_with_csr_rw.602923140 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_errors.822935791
Short name T1202
Test name
Test status
Simulation time 52146625 ps
CPU time 3.15 seconds
Started May 21 01:56:22 PM PDT 24
Finished May 21 01:56:27 PM PDT 24
Peak memory 216764 kb
Host smart-85ddfd02-d3f5-49ed-b107-65e694043fe1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822935791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.822935791 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/11.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.2798678213
Short name T1226
Test name
Test status
Simulation time 189799544 ps
CPU time 2.9 seconds
Started May 21 01:56:22 PM PDT 24
Finished May 21 01:56:27 PM PDT 24
Peak memory 216608 kb
Host smart-2bd8071f-506c-4017-bd28-76581c2ccc87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798678213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.2798
678213 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2570487455
Short name T1168
Test name
Test status
Simulation time 39906711 ps
CPU time 1.66 seconds
Started May 21 01:56:29 PM PDT 24
Finished May 21 01:56:33 PM PDT 24
Peak memory 218748 kb
Host smart-8e49e621-1fc5-4920-a139-30dbe83a72a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570487455 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.2570487455 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_rw.2783864795
Short name T1090
Test name
Test status
Simulation time 431133402 ps
CPU time 1.29 seconds
Started May 21 01:56:29 PM PDT 24
Finished May 21 01:56:32 PM PDT 24
Peak memory 216652 kb
Host smart-14270673-09da-4d3a-a5a9-85464f55f152
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783864795 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.2783864795 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_intr_test.706450912
Short name T1193
Test name
Test status
Simulation time 38878319 ps
CPU time 0.8 seconds
Started May 21 01:56:28 PM PDT 24
Finished May 21 01:56:30 PM PDT 24
Peak memory 216432 kb
Host smart-91cb7939-24ae-445b-bb85-580144093699
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706450912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.706450912 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/12.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3587658313
Short name T1187
Test name
Test status
Simulation time 74231754 ps
CPU time 2.37 seconds
Started May 21 01:56:27 PM PDT 24
Finished May 21 01:56:30 PM PDT 24
Peak memory 216632 kb
Host smart-2a598dc4-50ed-4d25-a967-78e39ad10432
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587658313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_cs
r_outstanding.3587658313 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.4139081545
Short name T83
Test name
Test status
Simulation time 44145949 ps
CPU time 1.29 seconds
Started May 21 01:56:33 PM PDT 24
Finished May 21 01:56:36 PM PDT 24
Peak memory 217976 kb
Host smart-9b316bb0-b4b1-400b-9c52-0c6be1682d1c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139081545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg
_errors.4139081545 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.4029935392
Short name T1169
Test name
Test status
Simulation time 487276994 ps
CPU time 2.61 seconds
Started May 21 01:56:27 PM PDT 24
Finished May 21 01:56:30 PM PDT 24
Peak memory 216640 kb
Host smart-b0eb2344-047a-4c66-97b9-037a62707542
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029935392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kma
c_shadow_reg_errors_with_csr_rw.4029935392 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_errors.2625547251
Short name T1194
Test name
Test status
Simulation time 160188638 ps
CPU time 2.54 seconds
Started May 21 01:56:29 PM PDT 24
Finished May 21 01:56:34 PM PDT 24
Peak memory 216800 kb
Host smart-3ff8a8c9-a697-4168-8c42-e1e67bceb713
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625547251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.2625547251 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.3011986625
Short name T161
Test name
Test status
Simulation time 950275320 ps
CPU time 5.19 seconds
Started May 21 01:56:28 PM PDT 24
Finished May 21 01:56:35 PM PDT 24
Peak memory 216728 kb
Host smart-7de027f1-66df-419a-81fd-8e1ec3d7f810
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011986625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.3011
986625 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.43846950
Short name T1167
Test name
Test status
Simulation time 733840984 ps
CPU time 1.62 seconds
Started May 21 01:56:33 PM PDT 24
Finished May 21 01:56:36 PM PDT 24
Peak memory 220580 kb
Host smart-9cfbf72e-b790-459a-a85e-3f49915d3972
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43846950 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.43846950 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_rw.2301474267
Short name T1075
Test name
Test status
Simulation time 115156074 ps
CPU time 0.94 seconds
Started May 21 01:56:32 PM PDT 24
Finished May 21 01:56:34 PM PDT 24
Peak memory 216444 kb
Host smart-85a0396a-19a7-4f75-b8df-44f331aac136
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301474267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.2301474267 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_intr_test.1199056727
Short name T1171
Test name
Test status
Simulation time 29929016 ps
CPU time 0.77 seconds
Started May 21 01:56:29 PM PDT 24
Finished May 21 01:56:32 PM PDT 24
Peak memory 216404 kb
Host smart-fe195661-e24d-411c-99d3-c6fb8237fa2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199056727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.1199056727 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3031581548
Short name T1215
Test name
Test status
Simulation time 106674281 ps
CPU time 2.62 seconds
Started May 21 01:56:30 PM PDT 24
Finished May 21 01:56:35 PM PDT 24
Peak memory 216664 kb
Host smart-60fbbf61-c1c2-4327-bdfe-310cf56d1d5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031581548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_cs
r_outstanding.3031581548 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3120864775
Short name T1209
Test name
Test status
Simulation time 61779699 ps
CPU time 1.21 seconds
Started May 21 01:56:28 PM PDT 24
Finished May 21 01:56:30 PM PDT 24
Peak memory 217272 kb
Host smart-d6a7090d-60c2-4d2d-8f28-78276c931bac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120864775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg
_errors.3120864775 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2551504972
Short name T86
Test name
Test status
Simulation time 45359061 ps
CPU time 1.61 seconds
Started May 21 01:56:29 PM PDT 24
Finished May 21 01:56:32 PM PDT 24
Peak memory 216696 kb
Host smart-f469f7a5-9ae6-4824-aa54-dbcf3c4cc3cf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551504972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kma
c_shadow_reg_errors_with_csr_rw.2551504972 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_errors.517980023
Short name T1101
Test name
Test status
Simulation time 46623731 ps
CPU time 1.62 seconds
Started May 21 01:56:30 PM PDT 24
Finished May 21 01:56:33 PM PDT 24
Peak memory 216772 kb
Host smart-710cb905-b00a-4370-93b3-2271c66cf1d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517980023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.517980023 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/13.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.1068981970
Short name T1177
Test name
Test status
Simulation time 26258562 ps
CPU time 1.68 seconds
Started May 21 01:56:29 PM PDT 24
Finished May 21 01:56:33 PM PDT 24
Peak memory 220100 kb
Host smart-18b2bb4a-3e2d-4dc3-b21c-b9f5544eeffd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068981970 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.1068981970 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_rw.826183225
Short name T1093
Test name
Test status
Simulation time 20713893 ps
CPU time 0.99 seconds
Started May 21 01:56:30 PM PDT 24
Finished May 21 01:56:33 PM PDT 24
Peak memory 216460 kb
Host smart-277766cd-3f68-48a2-bf43-9493d3c64283
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826183225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.826183225 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/14.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_intr_test.3682412918
Short name T1121
Test name
Test status
Simulation time 58829248 ps
CPU time 0.84 seconds
Started May 21 01:56:30 PM PDT 24
Finished May 21 01:56:33 PM PDT 24
Peak memory 216408 kb
Host smart-28816c7c-4008-4668-8d26-24aea1d7a83a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682412918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.3682412918 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.2274690568
Short name T1173
Test name
Test status
Simulation time 758577528 ps
CPU time 2.95 seconds
Started May 21 01:56:29 PM PDT 24
Finished May 21 01:56:34 PM PDT 24
Peak memory 216748 kb
Host smart-81c5dd50-91b4-42e8-8523-94540bc9e51a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274690568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_cs
r_outstanding.2274690568 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.2090962588
Short name T1157
Test name
Test status
Simulation time 65070291 ps
CPU time 1.84 seconds
Started May 21 01:56:31 PM PDT 24
Finished May 21 01:56:34 PM PDT 24
Peak memory 220116 kb
Host smart-0163ec41-d351-495b-a447-522af13bd5d0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090962588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kma
c_shadow_reg_errors_with_csr_rw.2090962588 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_errors.2308288681
Short name T1124
Test name
Test status
Simulation time 114005804 ps
CPU time 2.6 seconds
Started May 21 01:56:29 PM PDT 24
Finished May 21 01:56:34 PM PDT 24
Peak memory 216744 kb
Host smart-1a41f738-ccff-4f5a-931f-20c6f486a3fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308288681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.2308288681 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.3970410307
Short name T158
Test name
Test status
Simulation time 478195963 ps
CPU time 3.17 seconds
Started May 21 01:56:33 PM PDT 24
Finished May 21 01:56:38 PM PDT 24
Peak memory 216736 kb
Host smart-a1151405-5ef3-41bf-ae6f-e8358ddb706d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970410307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.3970
410307 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.3463823071
Short name T130
Test name
Test status
Simulation time 90327326 ps
CPU time 1.73 seconds
Started May 21 01:56:30 PM PDT 24
Finished May 21 01:56:34 PM PDT 24
Peak memory 217680 kb
Host smart-51792488-84e8-4a2c-bd32-b21517d2b11f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463823071 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.3463823071 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_rw.4135207798
Short name T134
Test name
Test status
Simulation time 330763046 ps
CPU time 1.03 seconds
Started May 21 01:56:29 PM PDT 24
Finished May 21 01:56:33 PM PDT 24
Peak memory 216356 kb
Host smart-814afbc9-2401-4752-b1ec-5427e87a5637
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135207798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.4135207798 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_intr_test.1094731013
Short name T1227
Test name
Test status
Simulation time 39919747 ps
CPU time 0.78 seconds
Started May 21 01:56:33 PM PDT 24
Finished May 21 01:56:35 PM PDT 24
Peak memory 216464 kb
Host smart-c85f794e-fc9f-4b8d-81c0-2aa12cfdfd24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094731013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.1094731013 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1360602002
Short name T1189
Test name
Test status
Simulation time 208569215 ps
CPU time 2.54 seconds
Started May 21 01:56:28 PM PDT 24
Finished May 21 01:56:32 PM PDT 24
Peak memory 216672 kb
Host smart-d6edab31-536e-45b9-ba72-13bb73edd9cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360602002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_cs
r_outstanding.1360602002 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2706288399
Short name T88
Test name
Test status
Simulation time 133746037 ps
CPU time 1.12 seconds
Started May 21 01:56:29 PM PDT 24
Finished May 21 01:56:32 PM PDT 24
Peak memory 216924 kb
Host smart-02a1b80f-dcd2-43ec-9cd9-0a09def4f250
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706288399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg
_errors.2706288399 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_errors.4223476842
Short name T1176
Test name
Test status
Simulation time 105221193 ps
CPU time 1.85 seconds
Started May 21 01:56:29 PM PDT 24
Finished May 21 01:56:33 PM PDT 24
Peak memory 216744 kb
Host smart-4c7479ef-3aaf-452e-b80d-7a425e2ba032
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223476842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.4223476842 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.2208398595
Short name T165
Test name
Test status
Simulation time 390873650 ps
CPU time 2.98 seconds
Started May 21 01:56:35 PM PDT 24
Finished May 21 01:56:39 PM PDT 24
Peak memory 216716 kb
Host smart-572d5602-a1ab-42cc-85ca-65873c6d7619
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208398595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.2208
398595 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.3386817286
Short name T133
Test name
Test status
Simulation time 179159034 ps
CPU time 1.76 seconds
Started May 21 01:56:29 PM PDT 24
Finished May 21 01:56:33 PM PDT 24
Peak memory 220768 kb
Host smart-52164775-5af6-4a62-b2ca-8c2acb48bafc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386817286 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.3386817286 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_rw.1381964906
Short name T1229
Test name
Test status
Simulation time 51201726 ps
CPU time 1.12 seconds
Started May 21 01:56:30 PM PDT 24
Finished May 21 01:56:33 PM PDT 24
Peak memory 216616 kb
Host smart-4ef9ec1f-1c65-4787-b55c-5a4bbdbe0515
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381964906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.1381964906 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_intr_test.3308933542
Short name T1170
Test name
Test status
Simulation time 40892845 ps
CPU time 0.79 seconds
Started May 21 01:56:33 PM PDT 24
Finished May 21 01:56:35 PM PDT 24
Peak memory 216464 kb
Host smart-b58552c2-f2ce-4082-8af8-ec72c0b8dfbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308933542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.3308933542 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.1255821623
Short name T1144
Test name
Test status
Simulation time 25486050 ps
CPU time 1.45 seconds
Started May 21 01:56:29 PM PDT 24
Finished May 21 01:56:33 PM PDT 24
Peak memory 216684 kb
Host smart-2da319ff-e1e6-4d34-b402-ec13e8fedea7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255821623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_cs
r_outstanding.1255821623 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.384777390
Short name T1213
Test name
Test status
Simulation time 122718866 ps
CPU time 1.8 seconds
Started May 21 01:56:30 PM PDT 24
Finished May 21 01:56:34 PM PDT 24
Peak memory 216972 kb
Host smart-48e62536-ec78-4baf-851c-50473b95fa7e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384777390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac
_shadow_reg_errors_with_csr_rw.384777390 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_errors.575777661
Short name T1072
Test name
Test status
Simulation time 58820543 ps
CPU time 3.09 seconds
Started May 21 01:56:33 PM PDT 24
Finished May 21 01:56:38 PM PDT 24
Peak memory 216776 kb
Host smart-684de7eb-ba77-48fa-befe-553673672ac8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575777661 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.575777661 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/16.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.2713357233
Short name T159
Test name
Test status
Simulation time 190295447 ps
CPU time 2.57 seconds
Started May 21 01:56:29 PM PDT 24
Finished May 21 01:56:34 PM PDT 24
Peak memory 216692 kb
Host smart-1726ebf0-23ca-44e3-b8ba-584bb9cf32b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713357233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.2713
357233 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.3039599079
Short name T1199
Test name
Test status
Simulation time 281023519 ps
CPU time 2.72 seconds
Started May 21 01:56:36 PM PDT 24
Finished May 21 01:56:41 PM PDT 24
Peak memory 222060 kb
Host smart-d265ef93-d2fd-44cc-a1e2-795a4bf3ce7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039599079 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.3039599079 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_rw.1416166362
Short name T1163
Test name
Test status
Simulation time 28474808 ps
CPU time 1.11 seconds
Started May 21 01:56:31 PM PDT 24
Finished May 21 01:56:34 PM PDT 24
Peak memory 216676 kb
Host smart-d47168aa-c62c-41c7-97f9-18340788c7bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416166362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.1416166362 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_intr_test.302623715
Short name T150
Test name
Test status
Simulation time 22186905 ps
CPU time 0.8 seconds
Started May 21 01:56:30 PM PDT 24
Finished May 21 01:56:33 PM PDT 24
Peak memory 216384 kb
Host smart-978126de-9cb2-45b8-b78c-d05591d81694
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302623715 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.302623715 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/17.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.206945933
Short name T1191
Test name
Test status
Simulation time 456802792 ps
CPU time 2.81 seconds
Started May 21 01:56:32 PM PDT 24
Finished May 21 01:56:36 PM PDT 24
Peak memory 216720 kb
Host smart-c856e0ef-b77a-4174-8e3e-b8b2c3589529
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206945933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_csr
_outstanding.206945933 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.122151985
Short name T1086
Test name
Test status
Simulation time 140773400 ps
CPU time 3.01 seconds
Started May 21 01:56:35 PM PDT 24
Finished May 21 01:56:39 PM PDT 24
Peak memory 220092 kb
Host smart-fa457df3-5041-43ce-9a91-7da5441f102a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122151985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac
_shadow_reg_errors_with_csr_rw.122151985 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_errors.2311764061
Short name T1218
Test name
Test status
Simulation time 71560672 ps
CPU time 1.39 seconds
Started May 21 01:56:28 PM PDT 24
Finished May 21 01:56:31 PM PDT 24
Peak memory 216760 kb
Host smart-22f13641-2424-47bb-b735-1d1de28a8821
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311764061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.2311764061 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.1626794780
Short name T1148
Test name
Test status
Simulation time 124210079 ps
CPU time 2.93 seconds
Started May 21 01:56:34 PM PDT 24
Finished May 21 01:56:38 PM PDT 24
Peak memory 216744 kb
Host smart-f4bcac39-bf87-47dd-9364-9b22220583d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626794780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.1626
794780 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2148512151
Short name T1095
Test name
Test status
Simulation time 249168370 ps
CPU time 2.41 seconds
Started May 21 01:56:34 PM PDT 24
Finished May 21 01:56:38 PM PDT 24
Peak memory 220832 kb
Host smart-955d940b-bd7a-4f91-bf33-10734dd5e8cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148512151 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.2148512151 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_rw.2101812168
Short name T1076
Test name
Test status
Simulation time 42800156 ps
CPU time 0.98 seconds
Started May 21 01:56:34 PM PDT 24
Finished May 21 01:56:36 PM PDT 24
Peak memory 216460 kb
Host smart-38afbdad-2b90-4266-b769-8e2bab7f0635
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101812168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.2101812168 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_intr_test.44489963
Short name T114
Test name
Test status
Simulation time 27742101 ps
CPU time 0.82 seconds
Started May 21 01:56:35 PM PDT 24
Finished May 21 01:56:37 PM PDT 24
Peak memory 216480 kb
Host smart-6d84abef-1cb0-4237-a8cb-8c858527faaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44489963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.44489963 +enable_mas
king=1 +sw_key_masked=0
Directory /workspace/18.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.3942609055
Short name T1102
Test name
Test status
Simulation time 242984899 ps
CPU time 2.07 seconds
Started May 21 01:56:33 PM PDT 24
Finished May 21 01:56:36 PM PDT 24
Peak memory 216720 kb
Host smart-527d7b95-ba2c-40aa-be9e-1883627d45da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942609055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_cs
r_outstanding.3942609055 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.406860841
Short name T1146
Test name
Test status
Simulation time 34740177 ps
CPU time 1.21 seconds
Started May 21 01:56:36 PM PDT 24
Finished May 21 01:56:39 PM PDT 24
Peak memory 216924 kb
Host smart-3a851986-07ba-41fc-9567-56610392c7cf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406860841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_
errors.406860841 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.3430011701
Short name T89
Test name
Test status
Simulation time 159317619 ps
CPU time 2.35 seconds
Started May 21 01:56:34 PM PDT 24
Finished May 21 01:56:38 PM PDT 24
Peak memory 219356 kb
Host smart-5f3ad74a-5177-45e4-a556-7031c1a70d84
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430011701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kma
c_shadow_reg_errors_with_csr_rw.3430011701 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_errors.3731107313
Short name T1149
Test name
Test status
Simulation time 124802823 ps
CPU time 3.12 seconds
Started May 21 01:56:35 PM PDT 24
Finished May 21 01:56:39 PM PDT 24
Peak memory 216804 kb
Host smart-644d2cc3-0b1d-4280-811b-49e6d06d43e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731107313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.3731107313 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.2434796591
Short name T166
Test name
Test status
Simulation time 2585176703 ps
CPU time 5.7 seconds
Started May 21 01:56:36 PM PDT 24
Finished May 21 01:56:44 PM PDT 24
Peak memory 216860 kb
Host smart-f23ebfa0-90fe-40fa-b9b6-576bd06baf78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434796591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.2434
796591 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.1507925650
Short name T1122
Test name
Test status
Simulation time 70926795 ps
CPU time 2.49 seconds
Started May 21 01:56:38 PM PDT 24
Finished May 21 01:56:43 PM PDT 24
Peak memory 221760 kb
Host smart-659041ef-5d0c-4c9a-a4a8-04af85ca35c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507925650 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.1507925650 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_rw.3521249047
Short name T1130
Test name
Test status
Simulation time 55359541 ps
CPU time 1 seconds
Started May 21 01:56:36 PM PDT 24
Finished May 21 01:56:39 PM PDT 24
Peak memory 216472 kb
Host smart-45df5ce6-a0b0-42bd-8eec-b78d8d04c3a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521249047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.3521249047 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_intr_test.4246773130
Short name T1183
Test name
Test status
Simulation time 29128669 ps
CPU time 0.8 seconds
Started May 21 01:56:36 PM PDT 24
Finished May 21 01:56:38 PM PDT 24
Peak memory 216388 kb
Host smart-7356c7a7-8965-46d2-a653-f4975a3e69c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246773130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.4246773130 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.1905460032
Short name T1078
Test name
Test status
Simulation time 31393223 ps
CPU time 1.41 seconds
Started May 21 01:56:36 PM PDT 24
Finished May 21 01:56:40 PM PDT 24
Peak memory 216724 kb
Host smart-17ec2366-183c-45d5-a13a-fd10b3873478
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905460032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_cs
r_outstanding.1905460032 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.138340751
Short name T1165
Test name
Test status
Simulation time 109308377 ps
CPU time 1.15 seconds
Started May 21 01:56:38 PM PDT 24
Finished May 21 01:56:41 PM PDT 24
Peak memory 217888 kb
Host smart-d5dd5139-3621-4728-acf0-2a7eb2dfc198
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138340751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_
errors.138340751 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.1063190881
Short name T1188
Test name
Test status
Simulation time 94918072 ps
CPU time 2.9 seconds
Started May 21 01:56:36 PM PDT 24
Finished May 21 01:56:40 PM PDT 24
Peak memory 219480 kb
Host smart-1fab97b5-be8b-4a07-b5f5-ac92696212d5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063190881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kma
c_shadow_reg_errors_with_csr_rw.1063190881 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_errors.3379019602
Short name T1223
Test name
Test status
Simulation time 111778713 ps
CPU time 1.78 seconds
Started May 21 01:56:36 PM PDT 24
Finished May 21 01:56:40 PM PDT 24
Peak memory 216800 kb
Host smart-4e765cd2-4aa3-443c-aa28-9c92feb79428
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379019602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.3379019602 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.2028284721
Short name T164
Test name
Test status
Simulation time 330498807 ps
CPU time 5.3 seconds
Started May 21 01:56:35 PM PDT 24
Finished May 21 01:56:42 PM PDT 24
Peak memory 216740 kb
Host smart-0c2c4b22-6f0c-4b40-a655-9f4278f8f205
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028284721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.2028
284721 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.202740176
Short name T1181
Test name
Test status
Simulation time 293018633 ps
CPU time 4.5 seconds
Started May 21 01:56:00 PM PDT 24
Finished May 21 01:56:05 PM PDT 24
Peak memory 216604 kb
Host smart-105477e0-585d-4e95-a3a8-68e14654a57c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202740176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.20274017
6 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.1023640494
Short name T1195
Test name
Test status
Simulation time 159553337 ps
CPU time 8.33 seconds
Started May 21 01:56:09 PM PDT 24
Finished May 21 01:56:18 PM PDT 24
Peak memory 216672 kb
Host smart-4c6e663a-ec87-44e0-88b2-507b5b9fbf8c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023640494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.1023640
494 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.4076564658
Short name T115
Test name
Test status
Simulation time 31485861 ps
CPU time 1.24 seconds
Started May 21 01:56:03 PM PDT 24
Finished May 21 01:56:05 PM PDT 24
Peak memory 216680 kb
Host smart-a87de34b-809d-41c5-b190-2dda712d566a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076564658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.4076564
658 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.4261836114
Short name T1231
Test name
Test status
Simulation time 112968347 ps
CPU time 2.27 seconds
Started May 21 01:56:09 PM PDT 24
Finished May 21 01:56:12 PM PDT 24
Peak memory 221564 kb
Host smart-ce99b63f-15f3-4dac-b04a-8b3f1d7bd660
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261836114 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.4261836114 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_rw.3053813309
Short name T1117
Test name
Test status
Simulation time 21779360 ps
CPU time 0.92 seconds
Started May 21 01:56:09 PM PDT 24
Finished May 21 01:56:11 PM PDT 24
Peak memory 216500 kb
Host smart-dd5f8dfd-8707-410b-8fa5-e3106af82059
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053813309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.3053813309 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_intr_test.3751724731
Short name T1142
Test name
Test status
Simulation time 21815574 ps
CPU time 0.8 seconds
Started May 21 01:56:03 PM PDT 24
Finished May 21 01:56:04 PM PDT 24
Peak memory 216492 kb
Host smart-10604200-bd3d-40e9-840a-dafe7b247b00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751724731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.3751724731 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.2866929782
Short name T125
Test name
Test status
Simulation time 63613206 ps
CPU time 1.62 seconds
Started May 21 01:56:01 PM PDT 24
Finished May 21 01:56:03 PM PDT 24
Peak memory 216736 kb
Host smart-245a27a1-6846-4d06-b23e-be603a287639
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866929782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partia
l_access.2866929782 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_walk.3948563561
Short name T1174
Test name
Test status
Simulation time 83087561 ps
CPU time 0.72 seconds
Started May 21 01:55:59 PM PDT 24
Finished May 21 01:56:01 PM PDT 24
Peak memory 216356 kb
Host smart-b742f058-b2c9-4098-973b-6bae1cfef692
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948563561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.3948563561
+enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.3415341654
Short name T1133
Test name
Test status
Simulation time 71997852 ps
CPU time 2.2 seconds
Started May 21 01:56:01 PM PDT 24
Finished May 21 01:56:04 PM PDT 24
Peak memory 216632 kb
Host smart-2b438851-7771-4678-9027-9090eb774696
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415341654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr
_outstanding.3415341654 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.869202378
Short name T81
Test name
Test status
Simulation time 300841553 ps
CPU time 1.54 seconds
Started May 21 01:55:57 PM PDT 24
Finished May 21 01:55:59 PM PDT 24
Peak memory 217924 kb
Host smart-573659b3-9d98-4286-86d6-51e655c270c1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869202378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_e
rrors.869202378 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.4236538268
Short name T1190
Test name
Test status
Simulation time 746378678 ps
CPU time 2.79 seconds
Started May 21 01:55:57 PM PDT 24
Finished May 21 01:56:01 PM PDT 24
Peak memory 220108 kb
Host smart-325e0709-7ea0-49cf-a64d-688c91b7ab2a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236538268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac
_shadow_reg_errors_with_csr_rw.4236538268 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_errors.4265505996
Short name T1212
Test name
Test status
Simulation time 36951922 ps
CPU time 1.96 seconds
Started May 21 01:56:01 PM PDT 24
Finished May 21 01:56:03 PM PDT 24
Peak memory 216768 kb
Host smart-7b7a1980-ba5e-4947-b120-29699e886f7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265505996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.4265505996 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.3302469115
Short name T1225
Test name
Test status
Simulation time 242399613 ps
CPU time 3.01 seconds
Started May 21 01:55:59 PM PDT 24
Finished May 21 01:56:03 PM PDT 24
Peak memory 216700 kb
Host smart-46811534-15c4-4599-a1bc-bc1709f70beb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302469115 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.33024
69115 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.kmac_intr_test.3491580838
Short name T1214
Test name
Test status
Simulation time 51691233 ps
CPU time 0.81 seconds
Started May 21 01:56:35 PM PDT 24
Finished May 21 01:56:38 PM PDT 24
Peak memory 216408 kb
Host smart-9a0bfbe0-a548-4709-ae77-e2b974c52d68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491580838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.3491580838 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.kmac_intr_test.261086959
Short name T1136
Test name
Test status
Simulation time 15194328 ps
CPU time 0.88 seconds
Started May 21 01:56:36 PM PDT 24
Finished May 21 01:56:39 PM PDT 24
Peak memory 216476 kb
Host smart-ea2d43c2-61a0-4d96-b807-9af8e5910df9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261086959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.261086959 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/21.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.kmac_intr_test.1022586057
Short name T153
Test name
Test status
Simulation time 13631119 ps
CPU time 0.78 seconds
Started May 21 01:56:37 PM PDT 24
Finished May 21 01:56:40 PM PDT 24
Peak memory 216424 kb
Host smart-6b437d85-52be-46dc-86d1-ce43e0a96f84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022586057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.1022586057 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.kmac_intr_test.3970123866
Short name T1116
Test name
Test status
Simulation time 23801688 ps
CPU time 0.86 seconds
Started May 21 01:56:37 PM PDT 24
Finished May 21 01:56:40 PM PDT 24
Peak memory 216392 kb
Host smart-3ab7e12a-9ef2-4a5b-80ce-5788fbdd0006
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970123866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.3970123866 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.kmac_intr_test.2440725393
Short name T1164
Test name
Test status
Simulation time 22463761 ps
CPU time 0.79 seconds
Started May 21 01:56:38 PM PDT 24
Finished May 21 01:56:41 PM PDT 24
Peak memory 216428 kb
Host smart-4b4915ca-b986-4acf-91a2-70f093aa1be4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440725393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.2440725393 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.kmac_intr_test.1917330088
Short name T1145
Test name
Test status
Simulation time 12746084 ps
CPU time 0.82 seconds
Started May 21 01:56:41 PM PDT 24
Finished May 21 01:56:45 PM PDT 24
Peak memory 216436 kb
Host smart-c3d19412-4c7f-4ae4-b214-5c1041b52977
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917330088 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.1917330088 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.kmac_intr_test.2259995944
Short name T1220
Test name
Test status
Simulation time 44056690 ps
CPU time 0.83 seconds
Started May 21 01:56:33 PM PDT 24
Finished May 21 01:56:36 PM PDT 24
Peak memory 216472 kb
Host smart-5e74d7a0-1b1c-462b-b26d-4adcb600dd25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259995944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.2259995944 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.kmac_intr_test.3105510681
Short name T1211
Test name
Test status
Simulation time 13429586 ps
CPU time 0.81 seconds
Started May 21 01:56:41 PM PDT 24
Finished May 21 01:56:45 PM PDT 24
Peak memory 216448 kb
Host smart-65d1f04e-93fa-4c0d-b5e4-5737dcbab4da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105510681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.3105510681 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.kmac_intr_test.4268990307
Short name T1185
Test name
Test status
Simulation time 29081692 ps
CPU time 0.88 seconds
Started May 21 01:56:40 PM PDT 24
Finished May 21 01:56:44 PM PDT 24
Peak memory 216452 kb
Host smart-4092d038-d192-422e-9889-02e3d0e4cec4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268990307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.4268990307 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.1954402370
Short name T1097
Test name
Test status
Simulation time 486164463 ps
CPU time 9.94 seconds
Started May 21 01:56:00 PM PDT 24
Finished May 21 01:56:11 PM PDT 24
Peak memory 216656 kb
Host smart-40e31a15-1d22-47f9-8dbb-1752bb30ee3e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954402370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.1954402
370 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.2081721209
Short name T1089
Test name
Test status
Simulation time 1245351558 ps
CPU time 20.2 seconds
Started May 21 01:56:01 PM PDT 24
Finished May 21 01:56:22 PM PDT 24
Peak memory 216632 kb
Host smart-bd9cdfb9-5dd9-46d7-9f9f-93b9d57240d0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081721209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.2081721
209 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.1528201285
Short name T1091
Test name
Test status
Simulation time 54015151 ps
CPU time 0.99 seconds
Started May 21 01:56:03 PM PDT 24
Finished May 21 01:56:05 PM PDT 24
Peak memory 215932 kb
Host smart-dcb472d9-9483-4a70-9654-aded1df63031
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528201285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.1528201
285 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.3156622455
Short name T131
Test name
Test status
Simulation time 149655617 ps
CPU time 1.68 seconds
Started May 21 01:56:08 PM PDT 24
Finished May 21 01:56:11 PM PDT 24
Peak memory 218968 kb
Host smart-93d6f68e-f123-4caa-b4d3-cf2baa02f70f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156622455 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.3156622455 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_rw.3170613486
Short name T1203
Test name
Test status
Simulation time 22849359 ps
CPU time 1.15 seconds
Started May 21 01:56:02 PM PDT 24
Finished May 21 01:56:04 PM PDT 24
Peak memory 216664 kb
Host smart-ba1b2de4-c0fb-4074-a04e-771101cf1bdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170613486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.3170613486 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_intr_test.321693601
Short name T1126
Test name
Test status
Simulation time 51832695 ps
CPU time 0.86 seconds
Started May 21 01:56:02 PM PDT 24
Finished May 21 01:56:04 PM PDT 24
Peak memory 216400 kb
Host smart-2e6c9d0d-e10f-4d5c-a470-68862ebe18b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321693601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.321693601 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/3.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.311608505
Short name T126
Test name
Test status
Simulation time 18442630 ps
CPU time 1.24 seconds
Started May 21 01:56:03 PM PDT 24
Finished May 21 01:56:05 PM PDT 24
Peak memory 216160 kb
Host smart-708c05c0-e0f7-40fc-9267-44765eb09b9e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311608505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partial
_access.311608505 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_walk.2741629382
Short name T1127
Test name
Test status
Simulation time 45421923 ps
CPU time 0.73 seconds
Started May 21 01:56:09 PM PDT 24
Finished May 21 01:56:11 PM PDT 24
Peak memory 216480 kb
Host smart-c9992583-0ebc-42ca-8c9f-09270ec2a44f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741629382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.2741629382
+enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.1638134273
Short name T1221
Test name
Test status
Simulation time 121288766 ps
CPU time 2.8 seconds
Started May 21 01:56:01 PM PDT 24
Finished May 21 01:56:04 PM PDT 24
Peak memory 216632 kb
Host smart-bf6c565a-40c4-4dda-9b99-9cfd9575b7af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638134273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr
_outstanding.1638134273 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.4029302223
Short name T84
Test name
Test status
Simulation time 18367733 ps
CPU time 0.87 seconds
Started May 21 01:56:00 PM PDT 24
Finished May 21 01:56:02 PM PDT 24
Peak memory 216512 kb
Host smart-bbd81967-7ebb-4caf-a539-7b13b39a2b52
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029302223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_
errors.4029302223 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.3789176397
Short name T1113
Test name
Test status
Simulation time 96726218 ps
CPU time 1.54 seconds
Started May 21 01:55:59 PM PDT 24
Finished May 21 01:56:01 PM PDT 24
Peak memory 216684 kb
Host smart-67e4eb4d-94ce-4203-aa31-53ca2472d1d3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789176397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac
_shadow_reg_errors_with_csr_rw.3789176397 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_errors.845938539
Short name T1200
Test name
Test status
Simulation time 183910593 ps
CPU time 2.64 seconds
Started May 21 01:56:01 PM PDT 24
Finished May 21 01:56:04 PM PDT 24
Peak memory 216816 kb
Host smart-e4508c53-1531-401f-b1dc-d166575afe15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845938539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.845938539 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/3.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.1321067214
Short name T162
Test name
Test status
Simulation time 127528695 ps
CPU time 2.95 seconds
Started May 21 01:56:08 PM PDT 24
Finished May 21 01:56:12 PM PDT 24
Peak memory 216740 kb
Host smart-09fd1d82-35a4-4398-a0bc-c8fa1e670d19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321067214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.13210
67214 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.kmac_intr_test.2763310944
Short name T1198
Test name
Test status
Simulation time 57906916 ps
CPU time 0.82 seconds
Started May 21 01:56:41 PM PDT 24
Finished May 21 01:56:45 PM PDT 24
Peak memory 216440 kb
Host smart-3095d4c5-29a1-4dd1-a4fa-4e2373b9e325
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763310944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.2763310944 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.kmac_intr_test.3872057872
Short name T1084
Test name
Test status
Simulation time 13678687 ps
CPU time 0.81 seconds
Started May 21 01:56:38 PM PDT 24
Finished May 21 01:56:41 PM PDT 24
Peak memory 216440 kb
Host smart-91c57cb8-9b17-4364-94fb-5f6911d1e606
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872057872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.3872057872 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.kmac_intr_test.504515664
Short name T1196
Test name
Test status
Simulation time 36395759 ps
CPU time 0.82 seconds
Started May 21 01:56:39 PM PDT 24
Finished May 21 01:56:42 PM PDT 24
Peak memory 216460 kb
Host smart-33bca3d9-05e5-4d68-aebc-dabd1f24f988
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504515664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.504515664 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/32.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.kmac_intr_test.890451206
Short name T113
Test name
Test status
Simulation time 151720436 ps
CPU time 0.77 seconds
Started May 21 01:56:39 PM PDT 24
Finished May 21 01:56:41 PM PDT 24
Peak memory 216472 kb
Host smart-63c05faf-9dd8-4634-840c-48c140b4d27b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890451206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.890451206 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/33.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.kmac_intr_test.1830824974
Short name T1134
Test name
Test status
Simulation time 18036951 ps
CPU time 0.84 seconds
Started May 21 01:56:37 PM PDT 24
Finished May 21 01:56:40 PM PDT 24
Peak memory 216376 kb
Host smart-1699fe32-a701-4bb1-8176-10315fb31411
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830824974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.1830824974 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.kmac_intr_test.1911556175
Short name T1160
Test name
Test status
Simulation time 219336628 ps
CPU time 0.86 seconds
Started May 21 01:56:50 PM PDT 24
Finished May 21 01:56:52 PM PDT 24
Peak memory 216384 kb
Host smart-9424326b-0ab7-4bc5-91fa-560bc97d96b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911556175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.1911556175 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.kmac_intr_test.2381026717
Short name T1140
Test name
Test status
Simulation time 11431882 ps
CPU time 0.78 seconds
Started May 21 01:56:40 PM PDT 24
Finished May 21 01:56:43 PM PDT 24
Peak memory 216448 kb
Host smart-fcb42b1c-5d95-44e6-a802-e66505a8da53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381026717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.2381026717 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.kmac_intr_test.2311852350
Short name T1147
Test name
Test status
Simulation time 27969716 ps
CPU time 0.82 seconds
Started May 21 01:56:40 PM PDT 24
Finished May 21 01:56:44 PM PDT 24
Peak memory 216464 kb
Host smart-7565fa9e-367c-4f21-8d37-6f8940105fa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311852350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.2311852350 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.kmac_intr_test.1610472858
Short name T1119
Test name
Test status
Simulation time 22407564 ps
CPU time 0.78 seconds
Started May 21 01:56:42 PM PDT 24
Finished May 21 01:56:46 PM PDT 24
Peak memory 216464 kb
Host smart-99f86cfc-c3e6-4f98-a410-ff7c5a942add
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610472858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.1610472858 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.kmac_intr_test.3906253959
Short name T1154
Test name
Test status
Simulation time 16255920 ps
CPU time 0.83 seconds
Started May 21 01:56:50 PM PDT 24
Finished May 21 01:56:52 PM PDT 24
Peak memory 216476 kb
Host smart-28a7a075-5a6f-4f1d-933b-423d7ebaef06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906253959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.3906253959 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.584757369
Short name T1175
Test name
Test status
Simulation time 1402004190 ps
CPU time 9.79 seconds
Started May 21 01:56:10 PM PDT 24
Finished May 21 01:56:20 PM PDT 24
Peak memory 216616 kb
Host smart-fc745ba8-ceff-41b3-9573-ece2705e526b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584757369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.58475736
9 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.418948675
Short name T1107
Test name
Test status
Simulation time 998299431 ps
CPU time 10.3 seconds
Started May 21 01:56:08 PM PDT 24
Finished May 21 01:56:19 PM PDT 24
Peak memory 216632 kb
Host smart-82631a4e-c830-4571-8f93-417d7d5a1a3e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418948675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.41894867
5 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.188058367
Short name T1105
Test name
Test status
Simulation time 18039627 ps
CPU time 1.01 seconds
Started May 21 01:56:05 PM PDT 24
Finished May 21 01:56:07 PM PDT 24
Peak memory 216656 kb
Host smart-c5de2e20-65d6-4b56-8a21-ccf039a9c812
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188058367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.18805836
7 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.3324827765
Short name T1162
Test name
Test status
Simulation time 34533064 ps
CPU time 2.35 seconds
Started May 21 01:56:07 PM PDT 24
Finished May 21 01:56:10 PM PDT 24
Peak memory 221512 kb
Host smart-8b37f61e-d552-4e48-92ea-4d30eba73c4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324827765 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.3324827765 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_rw.4044317048
Short name T1210
Test name
Test status
Simulation time 29893696 ps
CPU time 1.01 seconds
Started May 21 01:56:05 PM PDT 24
Finished May 21 01:56:07 PM PDT 24
Peak memory 216500 kb
Host smart-18506e45-1cc6-4f7f-9e11-7106e6ed9eea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044317048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.4044317048 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_intr_test.2680340907
Short name T1172
Test name
Test status
Simulation time 14691637 ps
CPU time 0.84 seconds
Started May 21 01:56:08 PM PDT 24
Finished May 21 01:56:09 PM PDT 24
Peak memory 216412 kb
Host smart-ecdec2a4-201a-43bc-aad2-73151e122a5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680340907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.2680340907 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.1573156557
Short name T124
Test name
Test status
Simulation time 16033580 ps
CPU time 1.1 seconds
Started May 21 01:56:07 PM PDT 24
Finished May 21 01:56:09 PM PDT 24
Peak memory 216708 kb
Host smart-73d49b67-6aa5-478d-a3bb-b2e45a22a9ec
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573156557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partia
l_access.1573156557 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_walk.2467243509
Short name T1219
Test name
Test status
Simulation time 148863690 ps
CPU time 0.81 seconds
Started May 21 01:56:05 PM PDT 24
Finished May 21 01:56:07 PM PDT 24
Peak memory 216484 kb
Host smart-3d3fb743-4de3-49b3-a7d1-2b6163c97cb2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467243509 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.2467243509
+enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.2200620202
Short name T1111
Test name
Test status
Simulation time 270295189 ps
CPU time 1.67 seconds
Started May 21 01:56:07 PM PDT 24
Finished May 21 01:56:10 PM PDT 24
Peak memory 216748 kb
Host smart-39e0d089-062e-4447-b21e-e0f9a8addba9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200620202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr
_outstanding.2200620202 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.98203085
Short name T82
Test name
Test status
Simulation time 97734892 ps
CPU time 1.12 seconds
Started May 21 01:56:08 PM PDT 24
Finished May 21 01:56:10 PM PDT 24
Peak memory 217032 kb
Host smart-4b9b1b78-a196-46a7-b0e8-a043fdc7c59f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98203085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_er
rors.98203085 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.2809825397
Short name T1217
Test name
Test status
Simulation time 123962251 ps
CPU time 1.75 seconds
Started May 21 01:56:09 PM PDT 24
Finished May 21 01:56:11 PM PDT 24
Peak memory 219656 kb
Host smart-d0ddfeec-abc2-48ae-a864-11dde935479c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809825397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac
_shadow_reg_errors_with_csr_rw.2809825397 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_errors.1973385343
Short name T1073
Test name
Test status
Simulation time 101682632 ps
CPU time 2.75 seconds
Started May 21 01:56:06 PM PDT 24
Finished May 21 01:56:09 PM PDT 24
Peak memory 216748 kb
Host smart-acdd6884-d14a-4255-b975-6f67fc835eef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973385343 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.1973385343 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.2650989180
Short name T1112
Test name
Test status
Simulation time 57109118 ps
CPU time 2.52 seconds
Started May 21 01:56:07 PM PDT 24
Finished May 21 01:56:10 PM PDT 24
Peak memory 216744 kb
Host smart-33d213ed-1e93-43ac-99a9-a73a496ea09b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650989180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.26509
89180 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.kmac_intr_test.1615103177
Short name T151
Test name
Test status
Simulation time 87711021 ps
CPU time 0.8 seconds
Started May 21 01:56:42 PM PDT 24
Finished May 21 01:56:46 PM PDT 24
Peak memory 216340 kb
Host smart-ed76d864-f410-4002-9a3a-b8b4e224b471
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615103177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.1615103177 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.kmac_intr_test.2325400868
Short name T1087
Test name
Test status
Simulation time 29625389 ps
CPU time 0.79 seconds
Started May 21 01:56:42 PM PDT 24
Finished May 21 01:56:46 PM PDT 24
Peak memory 216460 kb
Host smart-72fbf8ee-7421-4c21-8c5e-f7a7b51a0bdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325400868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.2325400868 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.kmac_intr_test.122907498
Short name T1166
Test name
Test status
Simulation time 12335686 ps
CPU time 0.81 seconds
Started May 21 01:56:40 PM PDT 24
Finished May 21 01:56:42 PM PDT 24
Peak memory 216380 kb
Host smart-bd626723-c7f4-47f7-bab6-0dd7c76b0586
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122907498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.122907498 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/42.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.kmac_intr_test.2738808165
Short name T1085
Test name
Test status
Simulation time 13138981 ps
CPU time 0.79 seconds
Started May 21 01:56:43 PM PDT 24
Finished May 21 01:56:46 PM PDT 24
Peak memory 216424 kb
Host smart-87cae337-1fed-4438-91eb-f41093dab488
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738808165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.2738808165 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.kmac_intr_test.1735077330
Short name T1143
Test name
Test status
Simulation time 19203096 ps
CPU time 0.79 seconds
Started May 21 01:56:41 PM PDT 24
Finished May 21 01:56:45 PM PDT 24
Peak memory 216304 kb
Host smart-5cef52d2-955e-405d-91f7-564d2d82f4c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735077330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.1735077330 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.kmac_intr_test.3586355208
Short name T1138
Test name
Test status
Simulation time 18218730 ps
CPU time 0.83 seconds
Started May 21 01:56:43 PM PDT 24
Finished May 21 01:56:47 PM PDT 24
Peak memory 216420 kb
Host smart-bfa48d18-626b-4b75-841f-7436f9033e4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586355208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.3586355208 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.kmac_intr_test.2615631949
Short name T1110
Test name
Test status
Simulation time 12772932 ps
CPU time 0.79 seconds
Started May 21 01:56:40 PM PDT 24
Finished May 21 01:56:44 PM PDT 24
Peak memory 216484 kb
Host smart-9d269eb5-afd3-4fbf-84e2-414ed65111a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615631949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.2615631949 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.kmac_intr_test.2815781125
Short name T1139
Test name
Test status
Simulation time 54626419 ps
CPU time 0.85 seconds
Started May 21 01:56:42 PM PDT 24
Finished May 21 01:56:46 PM PDT 24
Peak memory 216496 kb
Host smart-6124fc9e-0434-4993-bbd9-e581bda8ddd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815781125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.2815781125 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.kmac_intr_test.488916392
Short name T1120
Test name
Test status
Simulation time 13144452 ps
CPU time 0.89 seconds
Started May 21 01:56:44 PM PDT 24
Finished May 21 01:56:47 PM PDT 24
Peak memory 216452 kb
Host smart-d3047b93-7019-49ad-b5f7-8b75289afb2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488916392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.488916392 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/48.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.kmac_intr_test.2384787939
Short name T1178
Test name
Test status
Simulation time 21660159 ps
CPU time 0.86 seconds
Started May 21 01:56:40 PM PDT 24
Finished May 21 01:56:43 PM PDT 24
Peak memory 216456 kb
Host smart-b1c5da36-12b0-497a-b18d-e6c69a8fb27c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384787939 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.2384787939 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.108769642
Short name T1083
Test name
Test status
Simulation time 64749285 ps
CPU time 1.7 seconds
Started May 21 01:56:12 PM PDT 24
Finished May 21 01:56:15 PM PDT 24
Peak memory 217772 kb
Host smart-77b1b2e6-886e-458c-bbfe-8500ddc4e3f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108769642 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.108769642 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_rw.3977324107
Short name T1098
Test name
Test status
Simulation time 58377234 ps
CPU time 1.08 seconds
Started May 21 01:56:19 PM PDT 24
Finished May 21 01:56:21 PM PDT 24
Peak memory 216656 kb
Host smart-8bf2902c-356d-4cde-8b28-706fee108f35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977324107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.3977324107 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_intr_test.1223788847
Short name T1096
Test name
Test status
Simulation time 25210092 ps
CPU time 0.81 seconds
Started May 21 01:56:19 PM PDT 24
Finished May 21 01:56:21 PM PDT 24
Peak memory 216340 kb
Host smart-ffa272cb-065a-40f0-b45c-e4ca94a38a2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223788847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.1223788847 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.1052290558
Short name T1197
Test name
Test status
Simulation time 94164392 ps
CPU time 1.59 seconds
Started May 21 01:56:09 PM PDT 24
Finished May 21 01:56:12 PM PDT 24
Peak memory 216728 kb
Host smart-17b46cca-f267-48bd-84f9-061abc83f78b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052290558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr
_outstanding.1052290558 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.880691401
Short name T1186
Test name
Test status
Simulation time 91253991 ps
CPU time 1.47 seconds
Started May 21 01:56:09 PM PDT 24
Finished May 21 01:56:11 PM PDT 24
Peak memory 217032 kb
Host smart-cf54d4e7-b018-4f5e-b5fe-e2c3e8cec16a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880691401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_e
rrors.880691401 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.2498859395
Short name T1192
Test name
Test status
Simulation time 925810472 ps
CPU time 2.94 seconds
Started May 21 01:56:08 PM PDT 24
Finished May 21 01:56:12 PM PDT 24
Peak memory 219412 kb
Host smart-fd3d5c23-112d-4a9b-9f31-f7be749873b9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498859395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac
_shadow_reg_errors_with_csr_rw.2498859395 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_errors.2868679549
Short name T1080
Test name
Test status
Simulation time 1209741813 ps
CPU time 3.49 seconds
Started May 21 01:56:19 PM PDT 24
Finished May 21 01:56:23 PM PDT 24
Peak memory 216768 kb
Host smart-f6a7a797-ebdd-45ae-9153-ed292a9f4a3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868679549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.2868679549 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.574920151
Short name T1103
Test name
Test status
Simulation time 251013723 ps
CPU time 2.33 seconds
Started May 21 01:56:15 PM PDT 24
Finished May 21 01:56:18 PM PDT 24
Peak memory 221684 kb
Host smart-cfccf848-2d86-4349-a9f3-ca240aa1d778
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574920151 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.574920151 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_rw.1700431654
Short name T146
Test name
Test status
Simulation time 22295916 ps
CPU time 0.98 seconds
Started May 21 01:56:12 PM PDT 24
Finished May 21 01:56:13 PM PDT 24
Peak memory 216484 kb
Host smart-17ea1813-7b8a-4c90-811c-bf14dd77b1f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700431654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.1700431654 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_intr_test.4240737313
Short name T1156
Test name
Test status
Simulation time 20986291 ps
CPU time 0.79 seconds
Started May 21 01:56:13 PM PDT 24
Finished May 21 01:56:15 PM PDT 24
Peak memory 216412 kb
Host smart-5ce022d6-2cdf-4bfd-bb10-7c6f9c00cde7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240737313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.4240737313 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.4278580827
Short name T1109
Test name
Test status
Simulation time 174777484 ps
CPU time 2.59 seconds
Started May 21 01:56:15 PM PDT 24
Finished May 21 01:56:19 PM PDT 24
Peak memory 216696 kb
Host smart-7b12d9e7-7294-4155-8c64-b87f3353b6f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278580827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr
_outstanding.4278580827 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.2948554236
Short name T1228
Test name
Test status
Simulation time 128885312 ps
CPU time 2.15 seconds
Started May 21 01:56:13 PM PDT 24
Finished May 21 01:56:16 PM PDT 24
Peak memory 216956 kb
Host smart-2c7d9ddb-f297-4e77-865f-8926c8e26a5f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948554236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac
_shadow_reg_errors_with_csr_rw.2948554236 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_errors.3847635335
Short name T1081
Test name
Test status
Simulation time 107502619 ps
CPU time 3.5 seconds
Started May 21 01:56:12 PM PDT 24
Finished May 21 01:56:17 PM PDT 24
Peak memory 216740 kb
Host smart-cf18a0eb-4cad-4c49-a1a9-07d01eb8ebbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847635335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.3847635335 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.2317980297
Short name T1114
Test name
Test status
Simulation time 158937970 ps
CPU time 4.55 seconds
Started May 21 01:56:15 PM PDT 24
Finished May 21 01:56:20 PM PDT 24
Peak memory 216724 kb
Host smart-c104227b-1b0d-47a1-bc80-fb0e1359de68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317980297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.23179
80297 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.759252361
Short name T1151
Test name
Test status
Simulation time 44929731 ps
CPU time 1.68 seconds
Started May 21 01:56:15 PM PDT 24
Finished May 21 01:56:18 PM PDT 24
Peak memory 220328 kb
Host smart-baff63b3-1255-439e-ba33-56910a27cfea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759252361 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.759252361 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_rw.866998411
Short name T1106
Test name
Test status
Simulation time 24753520 ps
CPU time 1.03 seconds
Started May 21 01:56:12 PM PDT 24
Finished May 21 01:56:15 PM PDT 24
Peak memory 216468 kb
Host smart-bb410dca-29f4-4d04-87b3-c687c9fc373c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866998411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.866998411 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/7.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_intr_test.349499693
Short name T1129
Test name
Test status
Simulation time 109422001 ps
CPU time 0.79 seconds
Started May 21 01:56:19 PM PDT 24
Finished May 21 01:56:21 PM PDT 24
Peak memory 216460 kb
Host smart-a169b6d8-cd63-4d32-a240-2da9c77d9c98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349499693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.349499693 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/7.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3098727652
Short name T1079
Test name
Test status
Simulation time 53672796 ps
CPU time 1.64 seconds
Started May 21 01:56:17 PM PDT 24
Finished May 21 01:56:20 PM PDT 24
Peak memory 216696 kb
Host smart-b17e42ee-24ab-472b-87da-23237cc152dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098727652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr
_outstanding.3098727652 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2994595770
Short name T1152
Test name
Test status
Simulation time 425372154 ps
CPU time 1.47 seconds
Started May 21 01:56:13 PM PDT 24
Finished May 21 01:56:16 PM PDT 24
Peak memory 217096 kb
Host smart-131c2bff-8738-4050-bd4b-56f704f3279b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994595770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_
errors.2994595770 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.498500427
Short name T1184
Test name
Test status
Simulation time 96346755 ps
CPU time 2.55 seconds
Started May 21 01:56:13 PM PDT 24
Finished May 21 01:56:17 PM PDT 24
Peak memory 219468 kb
Host smart-4028c53d-6e91-43bc-86d2-3178c5ff7d08
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498500427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_
shadow_reg_errors_with_csr_rw.498500427 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_errors.814221079
Short name T1232
Test name
Test status
Simulation time 22707772 ps
CPU time 1.37 seconds
Started May 21 01:56:16 PM PDT 24
Finished May 21 01:56:20 PM PDT 24
Peak memory 216760 kb
Host smart-ebee4877-bcc4-4330-962b-d85b6afa29d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814221079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.814221079 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/7.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.1671897811
Short name T1099
Test name
Test status
Simulation time 232540964 ps
CPU time 2.79 seconds
Started May 21 01:56:17 PM PDT 24
Finished May 21 01:56:21 PM PDT 24
Peak memory 216712 kb
Host smart-8b3609cf-44de-415b-94bc-7c03c912d2cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671897811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.16718
97811 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.618900604
Short name T1125
Test name
Test status
Simulation time 23683271 ps
CPU time 1.47 seconds
Started May 21 01:56:13 PM PDT 24
Finished May 21 01:56:16 PM PDT 24
Peak memory 217772 kb
Host smart-31d40b56-5264-4edf-9692-ae1adcd45632
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618900604 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.618900604 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_rw.2189029634
Short name T1153
Test name
Test status
Simulation time 37516468 ps
CPU time 0.97 seconds
Started May 21 01:56:12 PM PDT 24
Finished May 21 01:56:14 PM PDT 24
Peak memory 216396 kb
Host smart-d3c7fdc3-e81e-439b-a9fd-d58ec89d969f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189029634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.2189029634 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_intr_test.178651849
Short name T1082
Test name
Test status
Simulation time 14867885 ps
CPU time 0.8 seconds
Started May 21 01:56:19 PM PDT 24
Finished May 21 01:56:21 PM PDT 24
Peak memory 216468 kb
Host smart-6c027a22-10ec-4708-9949-6b86c1996f0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178651849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.178651849 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/8.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.4149723903
Short name T1104
Test name
Test status
Simulation time 83723456 ps
CPU time 2.44 seconds
Started May 21 01:56:16 PM PDT 24
Finished May 21 01:56:19 PM PDT 24
Peak memory 216700 kb
Host smart-430624e8-91f8-4a43-a8bc-555862fa0645
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149723903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr
_outstanding.4149723903 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.4143634301
Short name T1141
Test name
Test status
Simulation time 115366801 ps
CPU time 1.12 seconds
Started May 21 01:56:16 PM PDT 24
Finished May 21 01:56:19 PM PDT 24
Peak memory 216960 kb
Host smart-a09efe6d-d04e-46e1-85b0-25f0fffd67b5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143634301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_
errors.4143634301 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.3409689581
Short name T1234
Test name
Test status
Simulation time 213676776 ps
CPU time 1.81 seconds
Started May 21 01:56:11 PM PDT 24
Finished May 21 01:56:14 PM PDT 24
Peak memory 216700 kb
Host smart-27483efc-c0ab-4020-9380-2e2028c16012
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409689581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac
_shadow_reg_errors_with_csr_rw.3409689581 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_errors.1097805643
Short name T1201
Test name
Test status
Simulation time 66318858 ps
CPU time 2.48 seconds
Started May 21 01:56:13 PM PDT 24
Finished May 21 01:56:17 PM PDT 24
Peak memory 216776 kb
Host smart-2954371b-9f8b-4e04-a84b-e59f39e6b483
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097805643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.1097805643 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.949888485
Short name T1179
Test name
Test status
Simulation time 184197651 ps
CPU time 4.04 seconds
Started May 21 01:56:12 PM PDT 24
Finished May 21 01:56:16 PM PDT 24
Peak memory 216784 kb
Host smart-3889b2d3-2294-4393-ac85-403426c73b46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949888485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.949888
485 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.3466545328
Short name T1235
Test name
Test status
Simulation time 56172199 ps
CPU time 1.74 seconds
Started May 21 01:56:13 PM PDT 24
Finished May 21 01:56:16 PM PDT 24
Peak memory 220156 kb
Host smart-d6c92aee-2e33-489b-82d4-2b8c870b9405
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466545328 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.3466545328 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_rw.3096164312
Short name T1137
Test name
Test status
Simulation time 58750376 ps
CPU time 0.97 seconds
Started May 21 01:56:17 PM PDT 24
Finished May 21 01:56:20 PM PDT 24
Peak memory 216452 kb
Host smart-5becce18-7c4f-4c24-bd32-8eec7a1d840a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096164312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.3096164312 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_intr_test.206063211
Short name T1155
Test name
Test status
Simulation time 22538401 ps
CPU time 0.78 seconds
Started May 21 01:56:19 PM PDT 24
Finished May 21 01:56:21 PM PDT 24
Peak memory 216404 kb
Host smart-78bc974a-c1e3-46c9-8427-70b1b1b4def1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206063211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.206063211 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/9.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2224058981
Short name T1204
Test name
Test status
Simulation time 166019062 ps
CPU time 2.45 seconds
Started May 21 01:56:11 PM PDT 24
Finished May 21 01:56:14 PM PDT 24
Peak memory 216748 kb
Host smart-6d2a99e9-4a66-4b4e-9268-b06f0828a7d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224058981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr
_outstanding.2224058981 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.3164389617
Short name T1216
Test name
Test status
Simulation time 30539699 ps
CPU time 1.02 seconds
Started May 21 01:56:13 PM PDT 24
Finished May 21 01:56:15 PM PDT 24
Peak memory 216460 kb
Host smart-42d9af90-d074-414b-b0ac-d60852399879
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164389617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_
errors.3164389617 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.115653072
Short name T85
Test name
Test status
Simulation time 51130664 ps
CPU time 2.42 seconds
Started May 21 01:56:14 PM PDT 24
Finished May 21 01:56:17 PM PDT 24
Peak memory 219180 kb
Host smart-658706b2-d98b-479f-819c-aa5cff66e9bb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115653072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_
shadow_reg_errors_with_csr_rw.115653072 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_errors.3022807492
Short name T1071
Test name
Test status
Simulation time 85322363 ps
CPU time 2.14 seconds
Started May 21 01:56:14 PM PDT 24
Finished May 21 01:56:17 PM PDT 24
Peak memory 216812 kb
Host smart-995b2a5f-d27f-4a1e-8c41-efc459c29b61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022807492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.3022807492 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.994882994
Short name T160
Test name
Test status
Simulation time 193000264 ps
CPU time 4.08 seconds
Started May 21 01:56:12 PM PDT 24
Finished May 21 01:56:17 PM PDT 24
Peak memory 216748 kb
Host smart-d67a2abf-1c40-410d-9578-2402bb719187
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994882994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.994882
994 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.kmac_app.3513385942
Short name T954
Test name
Test status
Simulation time 6410840801 ps
CPU time 402.33 seconds
Started May 21 12:53:10 PM PDT 24
Finished May 21 01:00:01 PM PDT 24
Peak memory 252444 kb
Host smart-ac56e3d6-4db1-4d59-a956-919f81da1348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513385942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.3513385942 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_app/latest

Test location /workspace/coverage/default/0.kmac_app_with_partial_data.3929135644
Short name T327
Test name
Test status
Simulation time 14427703963 ps
CPU time 393.43 seconds
Started May 21 12:53:28 PM PDT 24
Finished May 21 01:00:05 PM PDT 24
Peak memory 252688 kb
Host smart-e104eb1d-ee07-4440-8485-26269a013483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929135644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.3929135644 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/0.kmac_burst_write.327800455
Short name T913
Test name
Test status
Simulation time 1296483200 ps
CPU time 83.62 seconds
Started May 21 12:53:25 PM PDT 24
Finished May 21 12:54:52 PM PDT 24
Peak memory 226760 kb
Host smart-dafba83e-650d-4e3d-8efc-eb67a7f36949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327800455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.327800455 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_burst_write/latest

Test location /workspace/coverage/default/0.kmac_edn_timeout_error.1628960981
Short name T770
Test name
Test status
Simulation time 102505783 ps
CPU time 1.14 seconds
Started May 21 12:53:15 PM PDT 24
Finished May 21 12:53:23 PM PDT 24
Peak memory 218604 kb
Host smart-23683e5f-9181-43c1-9be1-597709d34e88
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1628960981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.1628960981 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_ready_error.1343372210
Short name T583
Test name
Test status
Simulation time 220299930 ps
CPU time 2.91 seconds
Started May 21 12:53:13 PM PDT 24
Finished May 21 12:53:24 PM PDT 24
Peak memory 226132 kb
Host smart-53c9f3f2-6d00-49e3-8e11-bd423308d92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343372210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.1343372210 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_refresh.1474936122
Short name T953
Test name
Test status
Simulation time 8354027982 ps
CPU time 200.33 seconds
Started May 21 12:53:11 PM PDT 24
Finished May 21 12:56:40 PM PDT 24
Peak memory 241856 kb
Host smart-6c4539f2-79db-47fa-a0f6-45cdf7743a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474936122 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.1474936122 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/0.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/0.kmac_error.3921966330
Short name T1029
Test name
Test status
Simulation time 14695314887 ps
CPU time 348.71 seconds
Started May 21 12:53:19 PM PDT 24
Finished May 21 12:59:13 PM PDT 24
Peak memory 257460 kb
Host smart-95b0807a-5cc9-4d40-8e11-b62f25cd2656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921966330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.3921966330 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_error/latest

Test location /workspace/coverage/default/0.kmac_key_error.3603448774
Short name T668
Test name
Test status
Simulation time 6187541144 ps
CPU time 9.8 seconds
Started May 21 12:53:12 PM PDT 24
Finished May 21 12:53:30 PM PDT 24
Peak memory 218604 kb
Host smart-4613c5a5-c0e0-43ca-bc12-11d3260a551a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603448774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.3603448774 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_key_error/latest

Test location /workspace/coverage/default/0.kmac_long_msg_and_output.4210776619
Short name T485
Test name
Test status
Simulation time 490366911906 ps
CPU time 1846.64 seconds
Started May 21 12:53:22 PM PDT 24
Finished May 21 01:24:13 PM PDT 24
Peak memory 345260 kb
Host smart-f6f7ea84-d291-407f-8615-df8659e3e92b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210776619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_an
d_output.4210776619 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/0.kmac_mubi.2972849237
Short name T900
Test name
Test status
Simulation time 16603525242 ps
CPU time 190.36 seconds
Started May 21 12:53:23 PM PDT 24
Finished May 21 12:56:38 PM PDT 24
Peak memory 242352 kb
Host smart-b587243c-4485-4e4d-a2d4-66883dd7200c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972849237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.2972849237 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mubi/latest

Test location /workspace/coverage/default/0.kmac_sec_cm.409776285
Short name T102
Test name
Test status
Simulation time 6401893372 ps
CPU time 88.59 seconds
Started May 21 12:53:24 PM PDT 24
Finished May 21 12:54:57 PM PDT 24
Peak memory 287792 kb
Host smart-b4b9edad-19d7-45a2-ba63-9d9937bd3f8a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409776285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.409776285 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/0.kmac_sec_cm/latest

Test location /workspace/coverage/default/0.kmac_sideload.1150035585
Short name T335
Test name
Test status
Simulation time 11294564942 ps
CPU time 449.99 seconds
Started May 21 12:53:14 PM PDT 24
Finished May 21 01:00:51 PM PDT 24
Peak memory 254224 kb
Host smart-e7afbdc6-e2b8-4cb7-9b40-077b7e693a47
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150035585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.1150035585 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_sideload/latest

Test location /workspace/coverage/default/0.kmac_smoke.930279418
Short name T888
Test name
Test status
Simulation time 3320164431 ps
CPU time 78.81 seconds
Started May 21 12:53:08 PM PDT 24
Finished May 21 12:54:34 PM PDT 24
Peak memory 226764 kb
Host smart-5c0d5603-f769-4976-b172-630f063cb15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930279418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.930279418 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_smoke/latest

Test location /workspace/coverage/default/0.kmac_stress_all.4190205192
Short name T865
Test name
Test status
Simulation time 83467004509 ps
CPU time 663.08 seconds
Started May 21 12:53:16 PM PDT 24
Finished May 21 01:04:26 PM PDT 24
Peak memory 300724 kb
Host smart-5a4c741c-637a-446f-8e4e-647d65de0a48
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4190205192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.4190205192 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all/latest

Test location /workspace/coverage/default/0.kmac_stress_all_with_rand_reset.1904622515
Short name T118
Test name
Test status
Simulation time 178178417331 ps
CPU time 994.33 seconds
Started May 21 12:53:23 PM PDT 24
Finished May 21 01:10:02 PM PDT 24
Peak memory 281284 kb
Host smart-6c2494ea-4d7c-4be8-91c3-fde2e626fc31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1904622515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all_with_rand_reset.1904622515 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac.3176835583
Short name T917
Test name
Test status
Simulation time 245871966 ps
CPU time 5.72 seconds
Started May 21 12:53:30 PM PDT 24
Finished May 21 12:53:39 PM PDT 24
Peak memory 226672 kb
Host smart-393daef7-3e8d-48a8-aa7f-87ac19658cf1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176835583 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.kmac_test_vectors_kmac.3176835583 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac_xof.2586289427
Short name T798
Test name
Test status
Simulation time 240635248 ps
CPU time 6.28 seconds
Started May 21 12:53:26 PM PDT 24
Finished May 21 12:53:36 PM PDT 24
Peak memory 226704 kb
Host smart-dda2f393-d7d8-4435-ad2f-7c9ba028c6eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586289427 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.kmac_test_vectors_kmac_xof.2586289427 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_224.2724095515
Short name T597
Test name
Test status
Simulation time 81163131707 ps
CPU time 2019.77 seconds
Started May 21 12:53:22 PM PDT 24
Finished May 21 01:27:07 PM PDT 24
Peak memory 388948 kb
Host smart-16d42b27-243a-43eb-abfe-9ca4887af387
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2724095515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.2724095515 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_256.759172125
Short name T224
Test name
Test status
Simulation time 21052435179 ps
CPU time 1775.82 seconds
Started May 21 12:53:29 PM PDT 24
Finished May 21 01:23:08 PM PDT 24
Peak memory 375172 kb
Host smart-7c41487b-5a70-487d-9383-dfcb4985bcb9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=759172125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.759172125 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_384.3586788681
Short name T446
Test name
Test status
Simulation time 109056555762 ps
CPU time 1560.95 seconds
Started May 21 12:53:11 PM PDT 24
Finished May 21 01:19:20 PM PDT 24
Peak memory 348300 kb
Host smart-d4b7419d-303b-4056-baf4-25b3663e518f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3586788681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.3586788681 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_512.474203558
Short name T286
Test name
Test status
Simulation time 30235341854 ps
CPU time 1118.24 seconds
Started May 21 12:53:22 PM PDT 24
Finished May 21 01:12:05 PM PDT 24
Peak memory 299116 kb
Host smart-2b0fae84-d3f7-44cd-ab68-191d857ba64b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=474203558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.474203558 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_128.4117483283
Short name T208
Test name
Test status
Simulation time 359772925522 ps
CPU time 5696.78 seconds
Started May 21 12:53:14 PM PDT 24
Finished May 21 02:28:19 PM PDT 24
Peak memory 653332 kb
Host smart-4da977c2-b5d8-4d64-81cd-6235535e3438
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4117483283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.4117483283 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_256.559774979
Short name T656
Test name
Test status
Simulation time 211006318636 ps
CPU time 4219.13 seconds
Started May 21 12:53:24 PM PDT 24
Finished May 21 02:03:48 PM PDT 24
Peak memory 567756 kb
Host smart-1e8f5e50-0c2d-46ff-a9db-9f0604cfdcfc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=559774979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.559774979 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/1.kmac_alert_test.2621162738
Short name T237
Test name
Test status
Simulation time 45683755 ps
CPU time 0.84 seconds
Started May 21 12:53:16 PM PDT 24
Finished May 21 12:53:23 PM PDT 24
Peak memory 218424 kb
Host smart-43ea5690-0ab5-4cd1-a964-8cfdf9d8e9b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621162738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.2621162738 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_alert_test/latest

Test location /workspace/coverage/default/1.kmac_app_with_partial_data.606747783
Short name T571
Test name
Test status
Simulation time 8913741377 ps
CPU time 252.23 seconds
Started May 21 12:53:21 PM PDT 24
Finished May 21 12:57:38 PM PDT 24
Peak memory 246360 kb
Host smart-217f8ea6-04f0-43cf-a4d6-e751e224ad65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606747783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.606747783 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/1.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/1.kmac_burst_write.95271859
Short name T994
Test name
Test status
Simulation time 30572053857 ps
CPU time 727.96 seconds
Started May 21 12:53:19 PM PDT 24
Finished May 21 01:05:32 PM PDT 24
Peak memory 243108 kb
Host smart-b07e31f2-31f2-46e5-a19d-a196498c7f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95271859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.95271859 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_burst_write/latest

Test location /workspace/coverage/default/1.kmac_edn_timeout_error.1556942176
Short name T69
Test name
Test status
Simulation time 44747995 ps
CPU time 1.16 seconds
Started May 21 12:53:18 PM PDT 24
Finished May 21 12:53:25 PM PDT 24
Peak memory 218796 kb
Host smart-875aa43a-946a-4283-a4be-b0d75eec7be2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1556942176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.1556942176 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_mode_error.2421487092
Short name T424
Test name
Test status
Simulation time 40753166 ps
CPU time 0.88 seconds
Started May 21 12:53:16 PM PDT 24
Finished May 21 12:53:23 PM PDT 24
Peak memory 220600 kb
Host smart-a4c60768-0fc9-4fe0-a823-bae3aac20e9b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2421487092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.2421487092 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_ready_error.1824684766
Short name T625
Test name
Test status
Simulation time 4467773888 ps
CPU time 12.54 seconds
Started May 21 12:53:30 PM PDT 24
Finished May 21 12:53:46 PM PDT 24
Peak memory 226720 kb
Host smart-ff2f859b-3758-41d3-bf0d-909082eb4bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824684766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.1824684766 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_refresh.2069309548
Short name T448
Test name
Test status
Simulation time 10074193462 ps
CPU time 136.07 seconds
Started May 21 12:53:13 PM PDT 24
Finished May 21 12:55:37 PM PDT 24
Peak memory 237844 kb
Host smart-a803f426-4eeb-43b7-a08f-2f9c4006183c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069309548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.2069309548 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/1.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/1.kmac_error.3533270738
Short name T288
Test name
Test status
Simulation time 106873315 ps
CPU time 7.73 seconds
Started May 21 12:53:12 PM PDT 24
Finished May 21 12:53:28 PM PDT 24
Peak memory 226824 kb
Host smart-196c72e7-3239-416b-8643-fefa697faf49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533270738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.3533270738 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_error/latest

Test location /workspace/coverage/default/1.kmac_key_error.4088649643
Short name T267
Test name
Test status
Simulation time 3270364707 ps
CPU time 9.63 seconds
Started May 21 12:53:13 PM PDT 24
Finished May 21 12:53:30 PM PDT 24
Peak memory 218556 kb
Host smart-55c4a3a5-78b8-4b6b-92e5-ddd41407323e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088649643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.4088649643 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_key_error/latest

Test location /workspace/coverage/default/1.kmac_lc_escalation.142447483
Short name T877
Test name
Test status
Simulation time 485818749 ps
CPU time 13.46 seconds
Started May 21 12:53:16 PM PDT 24
Finished May 21 12:53:36 PM PDT 24
Peak memory 235068 kb
Host smart-9d96a792-5e0b-42f0-b90f-108c33174be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142447483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.142447483 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_lc_escalation/latest

Test location /workspace/coverage/default/1.kmac_long_msg_and_output.145977934
Short name T632
Test name
Test status
Simulation time 14552263203 ps
CPU time 1482.74 seconds
Started May 21 12:53:15 PM PDT 24
Finished May 21 01:18:04 PM PDT 24
Peak memory 354144 kb
Host smart-da10b0ed-a356-4dcb-a253-02d11cf2dc1f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145977934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_and
_output.145977934 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/1.kmac_sideload.3071166277
Short name T233
Test name
Test status
Simulation time 53820250026 ps
CPU time 364.02 seconds
Started May 21 12:53:27 PM PDT 24
Finished May 21 12:59:34 PM PDT 24
Peak memory 247320 kb
Host smart-841e3371-1405-401a-ab91-e8d497913920
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071166277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.3071166277 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_sideload/latest

Test location /workspace/coverage/default/1.kmac_smoke.4286620920
Short name T764
Test name
Test status
Simulation time 205463110 ps
CPU time 6 seconds
Started May 21 12:53:22 PM PDT 24
Finished May 21 12:53:36 PM PDT 24
Peak memory 222504 kb
Host smart-d0910a4a-a5fa-41c1-9838-c440fa11d515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286620920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.4286620920 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_smoke/latest

Test location /workspace/coverage/default/1.kmac_stress_all.3016773255
Short name T713
Test name
Test status
Simulation time 71372445097 ps
CPU time 2656.63 seconds
Started May 21 12:53:15 PM PDT 24
Finished May 21 01:37:39 PM PDT 24
Peak memory 422180 kb
Host smart-a7214d39-cc20-4143-851d-1bad9fdb7df2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3016773255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.3016773255 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_stress_all/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac.3008259743
Short name T140
Test name
Test status
Simulation time 1047485607 ps
CPU time 6.05 seconds
Started May 21 12:53:25 PM PDT 24
Finished May 21 12:53:35 PM PDT 24
Peak memory 218636 kb
Host smart-7838ba1a-277d-4ab8-b3a6-d20be21257c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008259743 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.kmac_test_vectors_kmac.3008259743 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac_xof.1897103929
Short name T642
Test name
Test status
Simulation time 305700379 ps
CPU time 6.04 seconds
Started May 21 12:53:17 PM PDT 24
Finished May 21 12:53:29 PM PDT 24
Peak memory 218656 kb
Host smart-af6a6b2e-d18f-4a1a-bb0e-0e86d39778fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897103929 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.kmac_test_vectors_kmac_xof.1897103929 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_224.2893694238
Short name T231
Test name
Test status
Simulation time 98686796382 ps
CPU time 2208.06 seconds
Started May 21 12:53:15 PM PDT 24
Finished May 21 01:30:10 PM PDT 24
Peak memory 388532 kb
Host smart-3e768649-dbcb-4a84-b9e3-0cf8bba5dc5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2893694238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.2893694238 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_256.2505026761
Short name T910
Test name
Test status
Simulation time 158770037686 ps
CPU time 1985.04 seconds
Started May 21 12:53:24 PM PDT 24
Finished May 21 01:26:33 PM PDT 24
Peak memory 384052 kb
Host smart-a6fa158b-d77f-4e20-83a8-c040b14e1722
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2505026761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.2505026761 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_384.1503546490
Short name T763
Test name
Test status
Simulation time 60000102049 ps
CPU time 1640.59 seconds
Started May 21 12:53:15 PM PDT 24
Finished May 21 01:20:43 PM PDT 24
Peak memory 346520 kb
Host smart-9afa991e-d2ae-49b2-85fc-b20408710261
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1503546490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.1503546490 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_512.3864400593
Short name T943
Test name
Test status
Simulation time 554737220222 ps
CPU time 1382.35 seconds
Started May 21 12:53:14 PM PDT 24
Finished May 21 01:16:23 PM PDT 24
Peak memory 300740 kb
Host smart-9768c171-de73-4013-b28f-d4f040f4998a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3864400593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.3864400593 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_128.2827821144
Short name T445
Test name
Test status
Simulation time 1973394092396 ps
CPU time 6320.42 seconds
Started May 21 12:53:30 PM PDT 24
Finished May 21 02:38:54 PM PDT 24
Peak memory 650100 kb
Host smart-b30ab168-b70c-4e8b-bd9f-d8b7b035f9be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2827821144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.2827821144 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_256.2362242061
Short name T797
Test name
Test status
Simulation time 977479268542 ps
CPU time 4805.35 seconds
Started May 21 12:53:16 PM PDT 24
Finished May 21 02:13:28 PM PDT 24
Peak memory 589524 kb
Host smart-e151014e-7c9b-4bdc-9d8a-01d270d9879f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2362242061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.2362242061 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/10.kmac_alert_test.2020572271
Short name T553
Test name
Test status
Simulation time 20301700 ps
CPU time 0.84 seconds
Started May 21 12:54:10 PM PDT 24
Finished May 21 12:54:13 PM PDT 24
Peak memory 218508 kb
Host smart-8d5f877d-952e-4666-b481-1b9b377e36fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020572271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.2020572271 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_alert_test/latest

Test location /workspace/coverage/default/10.kmac_app.1086569463
Short name T635
Test name
Test status
Simulation time 580638050 ps
CPU time 13.04 seconds
Started May 21 12:53:53 PM PDT 24
Finished May 21 12:54:10 PM PDT 24
Peak memory 220624 kb
Host smart-199ac4f9-95ae-4537-83f2-666a716370f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086569463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.1086569463 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_app/latest

Test location /workspace/coverage/default/10.kmac_burst_write.383875584
Short name T265
Test name
Test status
Simulation time 14085761906 ps
CPU time 504.99 seconds
Started May 21 12:53:46 PM PDT 24
Finished May 21 01:02:14 PM PDT 24
Peak memory 232484 kb
Host smart-af02a8ad-9bab-47c5-9121-c75393bcc85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383875584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.383875584 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_burst_write/latest

Test location /workspace/coverage/default/10.kmac_edn_timeout_error.1693854004
Short name T410
Test name
Test status
Simulation time 287286625 ps
CPU time 23.82 seconds
Started May 21 12:53:53 PM PDT 24
Finished May 21 12:54:21 PM PDT 24
Peak memory 231384 kb
Host smart-911bec54-abf2-41c8-aaf2-fd9e22a8a247
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1693854004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.1693854004 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_mode_error.2253483726
Short name T73
Test name
Test status
Simulation time 175820935 ps
CPU time 1.23 seconds
Started May 21 12:54:02 PM PDT 24
Finished May 21 12:54:07 PM PDT 24
Peak memory 221800 kb
Host smart-7a025ce4-33fc-4fe1-9193-c99337f38819
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2253483726 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.2253483726 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_refresh.991239732
Short name T468
Test name
Test status
Simulation time 64456361151 ps
CPU time 428.93 seconds
Started May 21 12:53:47 PM PDT 24
Finished May 21 01:01:00 PM PDT 24
Peak memory 255836 kb
Host smart-a4014470-0579-4b00-b511-e1530e6c776d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991239732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.991239732 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/10.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/10.kmac_error.1369965201
Short name T613
Test name
Test status
Simulation time 3230536779 ps
CPU time 55.92 seconds
Started May 21 12:54:04 PM PDT 24
Finished May 21 12:55:03 PM PDT 24
Peak memory 243156 kb
Host smart-012337c3-2368-4620-9b92-6a4d1c4ce643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369965201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.1369965201 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_error/latest

Test location /workspace/coverage/default/10.kmac_key_error.1627771289
Short name T1018
Test name
Test status
Simulation time 3513356648 ps
CPU time 3.65 seconds
Started May 21 12:54:18 PM PDT 24
Finished May 21 12:54:26 PM PDT 24
Peak memory 218560 kb
Host smart-91301e5c-8533-4fb4-80da-cdd843b9e468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627771289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.1627771289 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_key_error/latest

Test location /workspace/coverage/default/10.kmac_long_msg_and_output.3749336956
Short name T213
Test name
Test status
Simulation time 22220390722 ps
CPU time 393.34 seconds
Started May 21 12:54:02 PM PDT 24
Finished May 21 01:00:38 PM PDT 24
Peak memory 253028 kb
Host smart-57786c16-d0c8-406b-8146-6064134871e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749336956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_a
nd_output.3749336956 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/10.kmac_sideload.1141881781
Short name T493
Test name
Test status
Simulation time 10986399698 ps
CPU time 337.75 seconds
Started May 21 12:53:50 PM PDT 24
Finished May 21 12:59:32 PM PDT 24
Peak memory 249012 kb
Host smart-75aaafca-8b56-4b69-9f3f-c19457fb63bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141881781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.1141881781 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_sideload/latest

Test location /workspace/coverage/default/10.kmac_smoke.2444995291
Short name T758
Test name
Test status
Simulation time 333409146 ps
CPU time 8.22 seconds
Started May 21 12:53:42 PM PDT 24
Finished May 21 12:53:52 PM PDT 24
Peak memory 222396 kb
Host smart-9ab45982-b24b-454c-84bf-8c1678221358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444995291 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.2444995291 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_smoke/latest

Test location /workspace/coverage/default/10.kmac_stress_all.2530871936
Short name T546
Test name
Test status
Simulation time 24558566371 ps
CPU time 1639.49 seconds
Started May 21 12:54:03 PM PDT 24
Finished May 21 01:21:25 PM PDT 24
Peak memory 405416 kb
Host smart-ba8e0450-b3c8-43e8-b298-ce0e2d2caf04
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2530871936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.2530871936 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_stress_all/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac.3427242952
Short name T303
Test name
Test status
Simulation time 3639413248 ps
CPU time 6.43 seconds
Started May 21 12:53:48 PM PDT 24
Finished May 21 12:53:58 PM PDT 24
Peak memory 219628 kb
Host smart-daad8b69-1e08-41b3-921c-525f3cd95986
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427242952 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.kmac_test_vectors_kmac.3427242952 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac_xof.1238222178
Short name T175
Test name
Test status
Simulation time 3109019322 ps
CPU time 5.6 seconds
Started May 21 12:54:06 PM PDT 24
Finished May 21 12:54:16 PM PDT 24
Peak memory 218720 kb
Host smart-1d1013a8-a150-4432-a43e-daa6e2c48fbf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238222178 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.kmac_test_vectors_kmac_xof.1238222178 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_224.2236377455
Short name T772
Test name
Test status
Simulation time 20723884219 ps
CPU time 1977.51 seconds
Started May 21 12:54:02 PM PDT 24
Finished May 21 01:27:03 PM PDT 24
Peak memory 401024 kb
Host smart-69a6dd31-77bb-4c98-bf24-e034ebf2cdd5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2236377455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_224.2236377455 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_256.2698934081
Short name T874
Test name
Test status
Simulation time 20541986187 ps
CPU time 1857.57 seconds
Started May 21 12:53:53 PM PDT 24
Finished May 21 01:24:55 PM PDT 24
Peak memory 396308 kb
Host smart-b5853631-f0a4-4355-98cb-9e010bfef3ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2698934081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_256.2698934081 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_384.1501476703
Short name T706
Test name
Test status
Simulation time 47867158142 ps
CPU time 1580.19 seconds
Started May 21 12:54:07 PM PDT 24
Finished May 21 01:20:31 PM PDT 24
Peak memory 343472 kb
Host smart-5e86910e-361d-417e-acf5-5307458db649
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1501476703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_384.1501476703 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_512.2425504139
Short name T259
Test name
Test status
Simulation time 27495399693 ps
CPU time 1113.76 seconds
Started May 21 12:53:48 PM PDT 24
Finished May 21 01:12:25 PM PDT 24
Peak memory 297544 kb
Host smart-35f28363-79b0-42f3-9172-54d9a7ab8310
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2425504139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_512.2425504139 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_shake_128.2509681590
Short name T447
Test name
Test status
Simulation time 181574043067 ps
CPU time 5713.24 seconds
Started May 21 12:54:15 PM PDT 24
Finished May 21 02:29:33 PM PDT 24
Peak memory 655092 kb
Host smart-9f325f77-bbe8-42bf-9bd4-befdcdd365b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2509681590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_128.2509681590 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_shake_256.492856893
Short name T712
Test name
Test status
Simulation time 602248083372 ps
CPU time 4719.99 seconds
Started May 21 12:53:53 PM PDT 24
Finished May 21 02:12:38 PM PDT 24
Peak memory 572152 kb
Host smart-8df865d2-8c0c-413b-a9e7-cc73d02386e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=492856893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_256.492856893 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/11.kmac_alert_test.507146336
Short name T605
Test name
Test status
Simulation time 17591772 ps
CPU time 0.85 seconds
Started May 21 12:54:08 PM PDT 24
Finished May 21 12:54:12 PM PDT 24
Peak memory 218484 kb
Host smart-33847de0-31dc-4381-a4df-4167462a4fe7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507146336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.507146336 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/11.kmac_alert_test/latest

Test location /workspace/coverage/default/11.kmac_app.754389398
Short name T1042
Test name
Test status
Simulation time 71096538 ps
CPU time 2.35 seconds
Started May 21 12:54:12 PM PDT 24
Finished May 21 12:54:17 PM PDT 24
Peak memory 218624 kb
Host smart-bb17c58f-1736-440a-91b1-c5acf9407307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754389398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.754389398 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_app/latest

Test location /workspace/coverage/default/11.kmac_burst_write.3698566306
Short name T658
Test name
Test status
Simulation time 71982059440 ps
CPU time 1338.89 seconds
Started May 21 12:54:02 PM PDT 24
Finished May 21 01:16:24 PM PDT 24
Peak memory 237344 kb
Host smart-f724a19c-7a08-47a4-979c-888761d9061d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698566306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.3698566306 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_burst_write/latest

Test location /workspace/coverage/default/11.kmac_edn_timeout_error.650268794
Short name T783
Test name
Test status
Simulation time 8444199614 ps
CPU time 32.37 seconds
Started May 21 12:53:57 PM PDT 24
Finished May 21 12:54:33 PM PDT 24
Peak memory 235508 kb
Host smart-7171eaf0-f3e5-4131-8941-ba2af46cfa13
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=650268794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.650268794 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_mode_error.246888932
Short name T313
Test name
Test status
Simulation time 32161860 ps
CPU time 1.17 seconds
Started May 21 12:54:12 PM PDT 24
Finished May 21 12:54:15 PM PDT 24
Peak memory 222252 kb
Host smart-b26ac6f7-c148-4fc1-bf7c-5a5e8677043c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=246888932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.246888932 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_refresh.1985328790
Short name T477
Test name
Test status
Simulation time 6475992751 ps
CPU time 14.77 seconds
Started May 21 12:54:16 PM PDT 24
Finished May 21 12:54:36 PM PDT 24
Peak memory 226768 kb
Host smart-f3150d92-7194-44df-b03d-f0d334ef67d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985328790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.1985328790 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/11.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/11.kmac_error.1270180901
Short name T709
Test name
Test status
Simulation time 666111517 ps
CPU time 28.65 seconds
Started May 21 12:53:52 PM PDT 24
Finished May 21 12:54:25 PM PDT 24
Peak memory 242596 kb
Host smart-434c7e89-9aee-4fec-a83b-329dd4d56ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270180901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.1270180901 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_error/latest

Test location /workspace/coverage/default/11.kmac_key_error.1786945069
Short name T98
Test name
Test status
Simulation time 3196184245 ps
CPU time 7.4 seconds
Started May 21 12:53:54 PM PDT 24
Finished May 21 12:54:06 PM PDT 24
Peak memory 218552 kb
Host smart-688bae02-f1cc-47cf-89bb-d4ba8441fc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786945069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.1786945069 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_key_error/latest

Test location /workspace/coverage/default/11.kmac_lc_escalation.1760475325
Short name T49
Test name
Test status
Simulation time 38295271 ps
CPU time 1.5 seconds
Started May 21 12:54:09 PM PDT 24
Finished May 21 12:54:14 PM PDT 24
Peak memory 219424 kb
Host smart-4acfa289-5c72-4f17-9ffe-499677073a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760475325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.1760475325 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/11.kmac_lc_escalation/latest

Test location /workspace/coverage/default/11.kmac_long_msg_and_output.3663777231
Short name T875
Test name
Test status
Simulation time 1025906351 ps
CPU time 48.27 seconds
Started May 21 12:54:07 PM PDT 24
Finished May 21 12:54:59 PM PDT 24
Peak memory 238676 kb
Host smart-094fcce0-a5cb-415e-8f1f-e1813ce4bb8c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663777231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_a
nd_output.3663777231 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/11.kmac_sideload.1368542292
Short name T454
Test name
Test status
Simulation time 13772934955 ps
CPU time 306.05 seconds
Started May 21 12:53:45 PM PDT 24
Finished May 21 12:58:55 PM PDT 24
Peak memory 246544 kb
Host smart-b984b2d9-3d6e-4dcb-a12a-a08c36cce4c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368542292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.1368542292 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_sideload/latest

Test location /workspace/coverage/default/11.kmac_smoke.4075742548
Short name T215
Test name
Test status
Simulation time 6736839651 ps
CPU time 61.92 seconds
Started May 21 12:54:06 PM PDT 24
Finished May 21 12:55:12 PM PDT 24
Peak memory 223104 kb
Host smart-0a279189-c539-479e-8612-0635a1b06346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075742548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.4075742548 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_smoke/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac.2248799535
Short name T270
Test name
Test status
Simulation time 1538733509 ps
CPU time 9.17 seconds
Started May 21 12:53:57 PM PDT 24
Finished May 21 12:54:10 PM PDT 24
Peak memory 218620 kb
Host smart-acd73448-e669-4e60-8687-42dc4d2957da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248799535 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.kmac_test_vectors_kmac.2248799535 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac_xof.2712352940
Short name T392
Test name
Test status
Simulation time 261584718 ps
CPU time 6.09 seconds
Started May 21 12:53:57 PM PDT 24
Finished May 21 12:54:06 PM PDT 24
Peak memory 226620 kb
Host smart-9d82226c-9b11-4917-9111-943399d6858f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712352940 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.kmac_test_vectors_kmac_xof.2712352940 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_256.2769488582
Short name T800
Test name
Test status
Simulation time 64087161967 ps
CPU time 2051.76 seconds
Started May 21 12:54:02 PM PDT 24
Finished May 21 01:28:17 PM PDT 24
Peak memory 385244 kb
Host smart-9eaf25cf-88d5-467f-b7ed-ea0105aa7768
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2769488582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_256.2769488582 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_384.565241413
Short name T893
Test name
Test status
Simulation time 135103101353 ps
CPU time 1293.6 seconds
Started May 21 12:54:05 PM PDT 24
Finished May 21 01:15:42 PM PDT 24
Peak memory 338120 kb
Host smart-b0a2baf5-2606-4ea6-a33f-b4cf504e44b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=565241413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_384.565241413 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_512.59742874
Short name T376
Test name
Test status
Simulation time 26225746282 ps
CPU time 1279.2 seconds
Started May 21 12:53:46 PM PDT 24
Finished May 21 01:15:09 PM PDT 24
Peak memory 303248 kb
Host smart-c6d57b27-40ad-4a93-b594-1cbf055a063e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=59742874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_512.59742874 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_shake_128.4158405797
Short name T992
Test name
Test status
Simulation time 604871859494 ps
CPU time 5844.07 seconds
Started May 21 12:54:06 PM PDT 24
Finished May 21 02:31:34 PM PDT 24
Peak memory 666216 kb
Host smart-3cd77f78-89cc-415d-870c-61c23bc959ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4158405797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_128.4158405797 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_shake_256.3210552088
Short name T543
Test name
Test status
Simulation time 191365796780 ps
CPU time 4276.65 seconds
Started May 21 12:53:54 PM PDT 24
Finished May 21 02:05:15 PM PDT 24
Peak memory 560968 kb
Host smart-6fb2ff20-1b09-4f56-8e6f-8d32c4ea33a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3210552088 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_256.3210552088 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/12.kmac_alert_test.3885781340
Short name T322
Test name
Test status
Simulation time 18096880 ps
CPU time 0.87 seconds
Started May 21 12:54:07 PM PDT 24
Finished May 21 12:54:12 PM PDT 24
Peak memory 220580 kb
Host smart-811c28e2-7944-4c53-9e74-798d40d118e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885781340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.3885781340 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_alert_test/latest

Test location /workspace/coverage/default/12.kmac_app.1065653321
Short name T882
Test name
Test status
Simulation time 2054586269 ps
CPU time 62.44 seconds
Started May 21 12:54:11 PM PDT 24
Finished May 21 12:55:16 PM PDT 24
Peak memory 228552 kb
Host smart-b4df613c-faab-42f6-8ba9-2d47d5b85d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065653321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.1065653321 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_app/latest

Test location /workspace/coverage/default/12.kmac_burst_write.3561167027
Short name T129
Test name
Test status
Simulation time 32488386644 ps
CPU time 771.66 seconds
Started May 21 12:53:58 PM PDT 24
Finished May 21 01:06:53 PM PDT 24
Peak memory 242480 kb
Host smart-e602f000-8eed-40ab-967d-3ce9bdafef4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561167027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.3561167027 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_burst_write/latest

Test location /workspace/coverage/default/12.kmac_edn_timeout_error.3497304685
Short name T859
Test name
Test status
Simulation time 41141574 ps
CPU time 1.1 seconds
Started May 21 12:53:55 PM PDT 24
Finished May 21 12:54:00 PM PDT 24
Peak memory 218476 kb
Host smart-7cd4a0ac-0f1a-46b2-b9c1-e30779cd8099
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3497304685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.3497304685 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_mode_error.97809656
Short name T338
Test name
Test status
Simulation time 2980839312 ps
CPU time 33.97 seconds
Started May 21 12:54:11 PM PDT 24
Finished May 21 12:54:47 PM PDT 24
Peak memory 226628 kb
Host smart-c687fadc-d512-4c7b-bf5e-60cece7b4854
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=97809656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.97809656 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_refresh.1167543362
Short name T555
Test name
Test status
Simulation time 8250367462 ps
CPU time 320.35 seconds
Started May 21 12:53:55 PM PDT 24
Finished May 21 12:59:20 PM PDT 24
Peak memory 250268 kb
Host smart-864de9c0-32f1-4b49-9236-4e8661204ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167543362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.1167543362 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/12.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/12.kmac_error.3926688246
Short name T908
Test name
Test status
Simulation time 412901285 ps
CPU time 10.27 seconds
Started May 21 12:54:12 PM PDT 24
Finished May 21 12:54:25 PM PDT 24
Peak memory 226628 kb
Host smart-07be5576-de85-4aaa-b886-a308198deb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926688246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.3926688246 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_error/latest

Test location /workspace/coverage/default/12.kmac_key_error.4022177509
Short name T971
Test name
Test status
Simulation time 12216534419 ps
CPU time 16.31 seconds
Started May 21 12:54:05 PM PDT 24
Finished May 21 12:54:25 PM PDT 24
Peak memory 218604 kb
Host smart-e760304f-ec45-4619-af24-22c91ece34ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022177509 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.4022177509 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_key_error/latest

Test location /workspace/coverage/default/12.kmac_lc_escalation.3861946248
Short name T15
Test name
Test status
Simulation time 3927243916 ps
CPU time 28.39 seconds
Started May 21 12:53:59 PM PDT 24
Finished May 21 12:54:30 PM PDT 24
Peak memory 235212 kb
Host smart-3e1c1725-ae06-444e-b1d8-e67e02ece727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861946248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.3861946248 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/12.kmac_lc_escalation/latest

Test location /workspace/coverage/default/12.kmac_long_msg_and_output.465407382
Short name T343
Test name
Test status
Simulation time 125068524368 ps
CPU time 1293.77 seconds
Started May 21 12:54:10 PM PDT 24
Finished May 21 01:15:47 PM PDT 24
Peak memory 328800 kb
Host smart-9a4d0953-3f86-4d85-ad2d-7c5ada2e42e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465407382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_an
d_output.465407382 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/12.kmac_sideload.2584761391
Short name T514
Test name
Test status
Simulation time 28353712029 ps
CPU time 262.28 seconds
Started May 21 12:54:13 PM PDT 24
Finished May 21 12:58:39 PM PDT 24
Peak memory 244456 kb
Host smart-b32ba870-d393-4a04-9f44-40eba6337256
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584761391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.2584761391 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_sideload/latest

Test location /workspace/coverage/default/12.kmac_smoke.3492453325
Short name T767
Test name
Test status
Simulation time 2724913032 ps
CPU time 66.43 seconds
Started May 21 12:53:53 PM PDT 24
Finished May 21 12:55:04 PM PDT 24
Peak memory 222512 kb
Host smart-7649afe7-96ee-4d13-b399-63fd21423b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492453325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.3492453325 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_smoke/latest

Test location /workspace/coverage/default/12.kmac_stress_all.1650549214
Short name T287
Test name
Test status
Simulation time 84803551256 ps
CPU time 2232.91 seconds
Started May 21 12:53:57 PM PDT 24
Finished May 21 01:31:13 PM PDT 24
Peak memory 434784 kb
Host smart-8b56337b-6309-43b1-a6ed-1f4d8a72795d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1650549214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.1650549214 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_stress_all/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac.3913275104
Short name T1060
Test name
Test status
Simulation time 206297981 ps
CPU time 5.37 seconds
Started May 21 12:53:54 PM PDT 24
Finished May 21 12:54:04 PM PDT 24
Peak memory 226596 kb
Host smart-51786ef6-e1f5-4db7-9cc6-c3142ba944ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913275104 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.kmac_test_vectors_kmac.3913275104 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac_xof.2754292870
Short name T771
Test name
Test status
Simulation time 408023466 ps
CPU time 6.26 seconds
Started May 21 12:53:53 PM PDT 24
Finished May 21 12:54:04 PM PDT 24
Peak memory 218624 kb
Host smart-40aea628-0b04-439a-ae49-100c0147f14c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754292870 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.kmac_test_vectors_kmac_xof.2754292870 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_224.1544580513
Short name T196
Test name
Test status
Simulation time 20608159473 ps
CPU time 2115.64 seconds
Started May 21 12:54:14 PM PDT 24
Finished May 21 01:29:32 PM PDT 24
Peak memory 397012 kb
Host smart-da9c4d5c-806d-4a3b-a88b-4534d297dc65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1544580513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_224.1544580513 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_256.3841464582
Short name T503
Test name
Test status
Simulation time 19010298522 ps
CPU time 2058.42 seconds
Started May 21 12:53:56 PM PDT 24
Finished May 21 01:28:18 PM PDT 24
Peak memory 385708 kb
Host smart-d86ffde6-6715-46a2-ae63-d294e2deaf84
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3841464582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_256.3841464582 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_384.977668047
Short name T703
Test name
Test status
Simulation time 49878020416 ps
CPU time 1523.11 seconds
Started May 21 12:54:05 PM PDT 24
Finished May 21 01:19:32 PM PDT 24
Peak memory 340328 kb
Host smart-b881421a-6c0e-4790-8f19-9a4c84bec376
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=977668047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_384.977668047 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_512.2285862520
Short name T109
Test name
Test status
Simulation time 75321448426 ps
CPU time 1289.7 seconds
Started May 21 12:53:53 PM PDT 24
Finished May 21 01:15:27 PM PDT 24
Peak memory 296276 kb
Host smart-a147c445-1735-4e13-b1e7-e9b284504987
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2285862520 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_512.2285862520 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_shake_256.1861512300
Short name T596
Test name
Test status
Simulation time 303995557191 ps
CPU time 4720.14 seconds
Started May 21 12:54:09 PM PDT 24
Finished May 21 02:12:52 PM PDT 24
Peak memory 561932 kb
Host smart-3fb99a1f-4c7f-43b6-bb11-788b046dda37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1861512300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_256.1861512300 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/13.kmac_alert_test.3458545772
Short name T369
Test name
Test status
Simulation time 66019052 ps
CPU time 0.89 seconds
Started May 21 12:53:59 PM PDT 24
Finished May 21 12:54:03 PM PDT 24
Peak memory 220748 kb
Host smart-fe2923c0-9279-4cf6-a209-1a67ab4a27e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458545772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.3458545772 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_alert_test/latest

Test location /workspace/coverage/default/13.kmac_app.200233419
Short name T972
Test name
Test status
Simulation time 25442641988 ps
CPU time 181.73 seconds
Started May 21 12:54:09 PM PDT 24
Finished May 21 12:57:14 PM PDT 24
Peak memory 243124 kb
Host smart-b9855d99-72fe-4920-9fd1-f1edaaa5d838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200233419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.200233419 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_app/latest

Test location /workspace/coverage/default/13.kmac_burst_write.973436595
Short name T341
Test name
Test status
Simulation time 6476794666 ps
CPU time 312.68 seconds
Started May 21 12:54:07 PM PDT 24
Finished May 21 12:59:23 PM PDT 24
Peak memory 229544 kb
Host smart-6d57a7dc-ec58-4881-a188-196c4e2549b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973436595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.973436595 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_burst_write/latest

Test location /workspace/coverage/default/13.kmac_edn_timeout_error.711405512
Short name T617
Test name
Test status
Simulation time 7470676146 ps
CPU time 48.36 seconds
Started May 21 12:54:01 PM PDT 24
Finished May 21 12:54:52 PM PDT 24
Peak memory 227880 kb
Host smart-f106f67b-b106-4c8a-bf98-5c1d0b133084
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=711405512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.711405512 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_mode_error.2133308434
Short name T686
Test name
Test status
Simulation time 48526380 ps
CPU time 1.3 seconds
Started May 21 12:54:07 PM PDT 24
Finished May 21 12:54:12 PM PDT 24
Peak memory 222112 kb
Host smart-7c720d9a-f381-4f2b-ab7b-f4f8dd0819c6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2133308434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.2133308434 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_refresh.4177311052
Short name T368
Test name
Test status
Simulation time 14643095021 ps
CPU time 176.24 seconds
Started May 21 12:54:10 PM PDT 24
Finished May 21 12:57:09 PM PDT 24
Peak memory 243228 kb
Host smart-cdd0aa13-74b2-47dd-a714-89c8b2803fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177311052 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.4177311052 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/13.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/13.kmac_error.84243056
Short name T479
Test name
Test status
Simulation time 63771780392 ps
CPU time 368.8 seconds
Started May 21 12:54:16 PM PDT 24
Finished May 21 01:00:30 PM PDT 24
Peak memory 259520 kb
Host smart-c53b87ab-321f-41b9-b62b-4acc78c8a5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84243056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.84243056 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_error/latest

Test location /workspace/coverage/default/13.kmac_key_error.638923543
Short name T331
Test name
Test status
Simulation time 2550511159 ps
CPU time 8.51 seconds
Started May 21 12:54:02 PM PDT 24
Finished May 21 12:54:13 PM PDT 24
Peak memory 218484 kb
Host smart-68bd0a12-2330-400e-a010-028942d48f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638923543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.638923543 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_key_error/latest

Test location /workspace/coverage/default/13.kmac_lc_escalation.1513831666
Short name T432
Test name
Test status
Simulation time 552770927 ps
CPU time 13.04 seconds
Started May 21 12:54:18 PM PDT 24
Finished May 21 12:54:36 PM PDT 24
Peak memory 229428 kb
Host smart-ffab680b-c8d1-419d-9ab3-5b9d46b65149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513831666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.1513831666 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/13.kmac_lc_escalation/latest

Test location /workspace/coverage/default/13.kmac_long_msg_and_output.1219764157
Short name T263
Test name
Test status
Simulation time 390918743404 ps
CPU time 3215.34 seconds
Started May 21 12:53:59 PM PDT 24
Finished May 21 01:47:37 PM PDT 24
Peak memory 460004 kb
Host smart-15efdb8d-7acb-4d6b-b79b-5448179dc57b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219764157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_a
nd_output.1219764157 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/13.kmac_sideload.3743601774
Short name T319
Test name
Test status
Simulation time 2960836837 ps
CPU time 60.69 seconds
Started May 21 12:54:11 PM PDT 24
Finished May 21 12:55:15 PM PDT 24
Peak memory 226928 kb
Host smart-541eb8ab-aede-4a0c-80ff-fdead64a0a9d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743601774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.3743601774 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_sideload/latest

Test location /workspace/coverage/default/13.kmac_smoke.601522775
Short name T662
Test name
Test status
Simulation time 826242000 ps
CPU time 33.64 seconds
Started May 21 12:54:18 PM PDT 24
Finished May 21 12:54:56 PM PDT 24
Peak memory 226696 kb
Host smart-870d3ccc-8eb4-4ee6-83a3-64c5cdf60427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601522775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.601522775 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_smoke/latest

Test location /workspace/coverage/default/13.kmac_stress_all.513055271
Short name T60
Test name
Test status
Simulation time 111641388271 ps
CPU time 1482.97 seconds
Started May 21 12:54:12 PM PDT 24
Finished May 21 01:18:59 PM PDT 24
Peak memory 357980 kb
Host smart-fab52933-2400-46aa-8e88-78b048a966f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=513055271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.513055271 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_stress_all/latest

Test location /workspace/coverage/default/13.kmac_stress_all_with_rand_reset.887732273
Short name T846
Test name
Test status
Simulation time 312302509617 ps
CPU time 1576.56 seconds
Started May 21 12:54:03 PM PDT 24
Finished May 21 01:20:22 PM PDT 24
Peak memory 333344 kb
Host smart-eebbfe41-71f4-41bd-ac56-e76863f71222
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=887732273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all_with_rand_reset.887732273 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac.552606132
Short name T738
Test name
Test status
Simulation time 266191648 ps
CPU time 5.96 seconds
Started May 21 12:54:06 PM PDT 24
Finished May 21 12:54:16 PM PDT 24
Peak memory 226680 kb
Host smart-5a40569a-7e09-464b-925c-348904b51081
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552606132 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.kmac_test_vectors_kmac.552606132 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac_xof.2330383837
Short name T786
Test name
Test status
Simulation time 847282838 ps
CPU time 5.88 seconds
Started May 21 12:53:59 PM PDT 24
Finished May 21 12:54:07 PM PDT 24
Peak memory 219560 kb
Host smart-2fad730d-96e8-4310-bb55-d7250d48cf6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330383837 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.kmac_test_vectors_kmac_xof.2330383837 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_224.2269803196
Short name T852
Test name
Test status
Simulation time 434119880689 ps
CPU time 2248.92 seconds
Started May 21 12:53:54 PM PDT 24
Finished May 21 01:31:27 PM PDT 24
Peak memory 395308 kb
Host smart-06564e71-e37c-4bdb-ba7b-8ba9ed7e4867
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2269803196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_224.2269803196 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_256.2125214087
Short name T719
Test name
Test status
Simulation time 62322137917 ps
CPU time 2149.22 seconds
Started May 21 12:53:57 PM PDT 24
Finished May 21 01:29:50 PM PDT 24
Peak memory 386532 kb
Host smart-abdabf9f-c7f2-442c-8b27-f083d73fb851
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2125214087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_256.2125214087 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_384.2229264502
Short name T433
Test name
Test status
Simulation time 14731034510 ps
CPU time 1305.41 seconds
Started May 21 12:54:05 PM PDT 24
Finished May 21 01:15:54 PM PDT 24
Peak memory 338200 kb
Host smart-eee17482-f15a-4451-8973-2e2778c2c0b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2229264502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_384.2229264502 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_512.2317950903
Short name T883
Test name
Test status
Simulation time 21273511376 ps
CPU time 1102.43 seconds
Started May 21 12:53:55 PM PDT 24
Finished May 21 01:12:22 PM PDT 24
Peak memory 297048 kb
Host smart-aa1750c3-e468-45c1-9159-c8337220f937
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2317950903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_512.2317950903 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_shake_128.2431485179
Short name T1067
Test name
Test status
Simulation time 520256272364 ps
CPU time 6015.22 seconds
Started May 21 12:54:12 PM PDT 24
Finished May 21 02:34:30 PM PDT 24
Peak memory 642800 kb
Host smart-008c0ffd-8248-4458-9478-bcd48b80c50d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2431485179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_128.2431485179 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_shake_256.4183254286
Short name T941
Test name
Test status
Simulation time 619892701058 ps
CPU time 4703.25 seconds
Started May 21 12:54:14 PM PDT 24
Finished May 21 02:12:43 PM PDT 24
Peak memory 566604 kb
Host smart-cce59fa7-da63-4256-8db6-90c5136462c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4183254286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_256.4183254286 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/14.kmac_alert_test.606570385
Short name T439
Test name
Test status
Simulation time 16129062 ps
CPU time 0.85 seconds
Started May 21 12:54:02 PM PDT 24
Finished May 21 12:54:07 PM PDT 24
Peak memory 218404 kb
Host smart-1c674483-bc22-4d4e-b401-d9496cabb2df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606570385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.606570385 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/14.kmac_alert_test/latest

Test location /workspace/coverage/default/14.kmac_app.3120530109
Short name T810
Test name
Test status
Simulation time 15769621774 ps
CPU time 278.04 seconds
Started May 21 12:54:10 PM PDT 24
Finished May 21 12:58:51 PM PDT 24
Peak memory 246232 kb
Host smart-c8549536-99ac-4b50-a824-2839b039e388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120530109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.3120530109 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_app/latest

Test location /workspace/coverage/default/14.kmac_burst_write.488440092
Short name T808
Test name
Test status
Simulation time 2045419003 ps
CPU time 91.84 seconds
Started May 21 12:54:01 PM PDT 24
Finished May 21 12:55:35 PM PDT 24
Peak memory 227520 kb
Host smart-48f22325-8b24-4480-8bd7-5878e601bbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488440092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.488440092 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_burst_write/latest

Test location /workspace/coverage/default/14.kmac_edn_timeout_error.1274107350
Short name T698
Test name
Test status
Simulation time 724288747 ps
CPU time 10.12 seconds
Started May 21 12:54:10 PM PDT 24
Finished May 21 12:54:23 PM PDT 24
Peak memory 222300 kb
Host smart-602b87b2-82f5-471b-bf6e-9464d16543c6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1274107350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.1274107350 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_mode_error.518694382
Short name T75
Test name
Test status
Simulation time 62899227 ps
CPU time 1.02 seconds
Started May 21 12:54:12 PM PDT 24
Finished May 21 12:54:16 PM PDT 24
Peak memory 221876 kb
Host smart-5a79d1d5-8264-4fec-9bbe-87554be36c39
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=518694382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.518694382 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_refresh.3612400230
Short name T531
Test name
Test status
Simulation time 18787921831 ps
CPU time 109.82 seconds
Started May 21 12:54:22 PM PDT 24
Finished May 21 12:56:15 PM PDT 24
Peak memory 232820 kb
Host smart-2cb99739-1dec-423a-9ae1-10ee41c1f083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612400230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.3612400230 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/14.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/14.kmac_error.1979433882
Short name T949
Test name
Test status
Simulation time 7415346104 ps
CPU time 153.99 seconds
Started May 21 12:54:06 PM PDT 24
Finished May 21 12:56:44 PM PDT 24
Peak memory 259504 kb
Host smart-3e7a4f4e-d1a0-403c-8137-e19c597952b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979433882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.1979433882 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_error/latest

Test location /workspace/coverage/default/14.kmac_key_error.4036447185
Short name T449
Test name
Test status
Simulation time 1883889875 ps
CPU time 3.55 seconds
Started May 21 12:54:09 PM PDT 24
Finished May 21 12:54:16 PM PDT 24
Peak memory 218452 kb
Host smart-092b0a5b-4875-4c98-8c33-a40e8ecca11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036447185 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.4036447185 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_key_error/latest

Test location /workspace/coverage/default/14.kmac_lc_escalation.913610531
Short name T296
Test name
Test status
Simulation time 253185490 ps
CPU time 1.64 seconds
Started May 21 12:54:02 PM PDT 24
Finished May 21 12:54:07 PM PDT 24
Peak memory 219520 kb
Host smart-49facd4e-9654-4dd0-b512-7a3ebab6370e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913610531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.913610531 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/14.kmac_lc_escalation/latest

Test location /workspace/coverage/default/14.kmac_long_msg_and_output.3519427256
Short name T243
Test name
Test status
Simulation time 183321492771 ps
CPU time 3250.1 seconds
Started May 21 12:54:01 PM PDT 24
Finished May 21 01:48:14 PM PDT 24
Peak memory 492760 kb
Host smart-5302e0a5-b7d5-4b49-883e-09bf26f4d8f2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519427256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_a
nd_output.3519427256 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/14.kmac_sideload.2138787855
Short name T1033
Test name
Test status
Simulation time 13434211542 ps
CPU time 434.47 seconds
Started May 21 12:54:13 PM PDT 24
Finished May 21 01:01:31 PM PDT 24
Peak memory 253376 kb
Host smart-a16a6de5-8c2c-44b1-91f6-3cec93cb4916
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138787855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.2138787855 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_sideload/latest

Test location /workspace/coverage/default/14.kmac_smoke.3233245124
Short name T475
Test name
Test status
Simulation time 797021292 ps
CPU time 11.7 seconds
Started May 21 12:54:08 PM PDT 24
Finished May 21 12:54:23 PM PDT 24
Peak memory 219000 kb
Host smart-a1eef145-8be8-4fc8-a186-513c5a10e7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233245124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.3233245124 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_smoke/latest

Test location /workspace/coverage/default/14.kmac_stress_all.466861197
Short name T759
Test name
Test status
Simulation time 88449452000 ps
CPU time 1712.37 seconds
Started May 21 12:54:00 PM PDT 24
Finished May 21 01:22:35 PM PDT 24
Peak memory 412052 kb
Host smart-52df882a-d373-4dd2-99d1-74aae5173c03
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=466861197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.466861197 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_stress_all/latest

Test location /workspace/coverage/default/14.kmac_stress_all_with_rand_reset.3397850036
Short name T120
Test name
Test status
Simulation time 274395058503 ps
CPU time 2578.47 seconds
Started May 21 12:54:16 PM PDT 24
Finished May 21 01:37:20 PM PDT 24
Peak memory 415520 kb
Host smart-978fc251-fa8d-4863-a696-919a0556a88e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3397850036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all_with_rand_reset.3397850036 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac.811985784
Short name T937
Test name
Test status
Simulation time 845384667 ps
CPU time 7 seconds
Started May 21 12:54:01 PM PDT 24
Finished May 21 12:54:10 PM PDT 24
Peak memory 218584 kb
Host smart-e46bee84-20c4-4d24-a1a5-8744b7f15498
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811985784 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.kmac_test_vectors_kmac.811985784 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac_xof.2285871565
Short name T413
Test name
Test status
Simulation time 204890072 ps
CPU time 6.03 seconds
Started May 21 12:54:15 PM PDT 24
Finished May 21 12:54:25 PM PDT 24
Peak memory 226712 kb
Host smart-8a818076-e98d-42f9-b4e5-cf201dce2b85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285871565 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.kmac_test_vectors_kmac_xof.2285871565 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_224.4085169695
Short name T1058
Test name
Test status
Simulation time 63086254169 ps
CPU time 2147.83 seconds
Started May 21 12:54:06 PM PDT 24
Finished May 21 01:29:58 PM PDT 24
Peak memory 383400 kb
Host smart-d58d70e4-ea20-46d6-b187-291155bba3ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4085169695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_224.4085169695 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_384.2399998171
Short name T1054
Test name
Test status
Simulation time 49379436707 ps
CPU time 1644.95 seconds
Started May 21 12:54:14 PM PDT 24
Finished May 21 01:21:44 PM PDT 24
Peak memory 339828 kb
Host smart-ef511d40-c20a-469f-a13f-353781701c16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2399998171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_384.2399998171 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_shake_128.2296478977
Short name T440
Test name
Test status
Simulation time 833908349911 ps
CPU time 5731.28 seconds
Started May 21 12:54:19 PM PDT 24
Finished May 21 02:29:55 PM PDT 24
Peak memory 638140 kb
Host smart-b34958da-0e31-4ee5-8aac-1e7fb6ad500e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2296478977 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_128.2296478977 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_shake_256.2636156402
Short name T792
Test name
Test status
Simulation time 234470881540 ps
CPU time 5215.09 seconds
Started May 21 12:54:01 PM PDT 24
Finished May 21 02:20:59 PM PDT 24
Peak memory 562880 kb
Host smart-2551c5e3-4743-4f52-a335-3bde3e3e9aa1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2636156402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_256.2636156402 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/15.kmac_alert_test.4009960510
Short name T394
Test name
Test status
Simulation time 50209725 ps
CPU time 0.81 seconds
Started May 21 12:54:06 PM PDT 24
Finished May 21 12:54:11 PM PDT 24
Peak memory 218520 kb
Host smart-dec3b388-6ec7-43f0-9219-9169f0c637ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009960510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.4009960510 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_alert_test/latest

Test location /workspace/coverage/default/15.kmac_app.3365190564
Short name T19
Test name
Test status
Simulation time 16990767555 ps
CPU time 204.29 seconds
Started May 21 12:54:00 PM PDT 24
Finished May 21 12:57:27 PM PDT 24
Peak memory 242204 kb
Host smart-89fb2769-354c-4e57-9c53-1deee8085336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365190564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.3365190564 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_app/latest

Test location /workspace/coverage/default/15.kmac_burst_write.2916978995
Short name T429
Test name
Test status
Simulation time 5366987832 ps
CPU time 341.9 seconds
Started May 21 12:54:14 PM PDT 24
Finished May 21 12:59:59 PM PDT 24
Peak memory 230228 kb
Host smart-0472eb77-ca8c-4afa-b68e-8b10a5b713d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916978995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.2916978995 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_burst_write/latest

Test location /workspace/coverage/default/15.kmac_edn_timeout_error.813202826
Short name T670
Test name
Test status
Simulation time 18262575 ps
CPU time 0.84 seconds
Started May 21 12:54:16 PM PDT 24
Finished May 21 12:54:22 PM PDT 24
Peak memory 218416 kb
Host smart-dd48d761-8820-49ab-88c4-c14c632144d7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=813202826 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.813202826 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_mode_error.4179298751
Short name T249
Test name
Test status
Simulation time 77974796 ps
CPU time 1.18 seconds
Started May 21 12:54:20 PM PDT 24
Finished May 21 12:54:25 PM PDT 24
Peak memory 222260 kb
Host smart-26675f63-6da7-4099-9f02-5e8105643741
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4179298751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.4179298751 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_refresh.1930664073
Short name T734
Test name
Test status
Simulation time 55715886248 ps
CPU time 377.7 seconds
Started May 21 12:54:07 PM PDT 24
Finished May 21 01:00:29 PM PDT 24
Peak memory 252632 kb
Host smart-64984da9-e7f6-4998-ac00-f77a0fcce1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930664073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.1930664073 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/15.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/15.kmac_error.2963607085
Short name T22
Test name
Test status
Simulation time 23672388374 ps
CPU time 406.46 seconds
Started May 21 12:54:18 PM PDT 24
Finished May 21 01:01:09 PM PDT 24
Peak memory 266736 kb
Host smart-c1e089c1-0370-4185-a4c8-7dc7337da9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963607085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.2963607085 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_error/latest

Test location /workspace/coverage/default/15.kmac_key_error.140089537
Short name T437
Test name
Test status
Simulation time 680012166 ps
CPU time 5.56 seconds
Started May 21 12:54:12 PM PDT 24
Finished May 21 12:54:21 PM PDT 24
Peak memory 218504 kb
Host smart-3ad845ce-8d7b-4d6f-9f1c-0eb3445e7bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140089537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.140089537 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_key_error/latest

Test location /workspace/coverage/default/15.kmac_lc_escalation.3022626147
Short name T76
Test name
Test status
Simulation time 38845438 ps
CPU time 1.32 seconds
Started May 21 12:54:14 PM PDT 24
Finished May 21 12:54:20 PM PDT 24
Peak memory 218620 kb
Host smart-9cf02357-808e-4d08-8920-0fe7b020ca53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022626147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.3022626147 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/15.kmac_lc_escalation/latest

Test location /workspace/coverage/default/15.kmac_long_msg_and_output.1623320998
Short name T180
Test name
Test status
Simulation time 96011817664 ps
CPU time 2493.79 seconds
Started May 21 12:54:27 PM PDT 24
Finished May 21 01:36:03 PM PDT 24
Peak memory 421464 kb
Host smart-feb70d8c-55fd-4c49-990e-377a0f94f055
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623320998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_a
nd_output.1623320998 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/15.kmac_sideload.3644290433
Short name T282
Test name
Test status
Simulation time 6101741210 ps
CPU time 516.41 seconds
Started May 21 12:54:09 PM PDT 24
Finished May 21 01:02:49 PM PDT 24
Peak memory 259872 kb
Host smart-79cecb0d-22be-450d-ac98-81aa82854dfd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644290433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.3644290433 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_sideload/latest

Test location /workspace/coverage/default/15.kmac_smoke.2876389661
Short name T467
Test name
Test status
Simulation time 1911220475 ps
CPU time 69.16 seconds
Started May 21 12:54:03 PM PDT 24
Finished May 21 12:55:15 PM PDT 24
Peak memory 226676 kb
Host smart-02a67cfc-b237-49be-a4dc-7e530d39ea04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876389661 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.2876389661 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_smoke/latest

Test location /workspace/coverage/default/15.kmac_stress_all.2591046152
Short name T823
Test name
Test status
Simulation time 28785253900 ps
CPU time 975.68 seconds
Started May 21 12:54:02 PM PDT 24
Finished May 21 01:10:21 PM PDT 24
Peak memory 324508 kb
Host smart-c41309c0-e526-4a24-9e7f-961fd7d3feab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2591046152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.2591046152 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_stress_all/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac.782587173
Short name T510
Test name
Test status
Simulation time 1238284831 ps
CPU time 6.26 seconds
Started May 21 12:54:12 PM PDT 24
Finished May 21 12:54:21 PM PDT 24
Peak memory 226676 kb
Host smart-11e9b07f-a33c-4ead-aa48-305080bb3e2f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782587173 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.kmac_test_vectors_kmac.782587173 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac_xof.1059887072
Short name T200
Test name
Test status
Simulation time 241486267 ps
CPU time 6.34 seconds
Started May 21 12:54:01 PM PDT 24
Finished May 21 12:54:10 PM PDT 24
Peak memory 218496 kb
Host smart-34db2f05-260e-4587-9b32-bdf8881d9a4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059887072 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.kmac_test_vectors_kmac_xof.1059887072 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_224.70036845
Short name T923
Test name
Test status
Simulation time 20546883196 ps
CPU time 1993.41 seconds
Started May 21 12:54:09 PM PDT 24
Finished May 21 01:27:26 PM PDT 24
Peak memory 396208 kb
Host smart-ecfb559f-1da3-4980-b8d6-d035cc1564c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=70036845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_224.70036845 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_256.2682585458
Short name T219
Test name
Test status
Simulation time 63054330087 ps
CPU time 2193.29 seconds
Started May 21 12:54:03 PM PDT 24
Finished May 21 01:30:39 PM PDT 24
Peak memory 389776 kb
Host smart-04967840-9464-4a2b-9971-45cfdd73e969
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2682585458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_256.2682585458 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_384.359473503
Short name T401
Test name
Test status
Simulation time 30074646429 ps
CPU time 1603.55 seconds
Started May 21 12:54:07 PM PDT 24
Finished May 21 01:20:55 PM PDT 24
Peak memory 344456 kb
Host smart-b74c134a-a1c3-43e3-b8d8-05efa3c0438f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=359473503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_384.359473503 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_512.1334978424
Short name T890
Test name
Test status
Simulation time 523020856613 ps
CPU time 1362.5 seconds
Started May 21 12:54:01 PM PDT 24
Finished May 21 01:16:46 PM PDT 24
Peak memory 297268 kb
Host smart-f0c9bc05-bd73-46ac-8747-d94005f12443
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1334978424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_512.1334978424 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_shake_128.2651857267
Short name T387
Test name
Test status
Simulation time 710364185239 ps
CPU time 6134.42 seconds
Started May 21 12:54:07 PM PDT 24
Finished May 21 02:36:26 PM PDT 24
Peak memory 668628 kb
Host smart-a1e08ab1-7728-4b29-9172-238c8078c6ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2651857267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_128.2651857267 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_shake_256.2390114585
Short name T189
Test name
Test status
Simulation time 249455604040 ps
CPU time 5302.15 seconds
Started May 21 12:54:01 PM PDT 24
Finished May 21 02:22:27 PM PDT 24
Peak memory 573816 kb
Host smart-5e80d914-91fc-4045-86d8-3545f6ca6b36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2390114585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_256.2390114585 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/16.kmac_alert_test.3614563790
Short name T961
Test name
Test status
Simulation time 18748945 ps
CPU time 0.85 seconds
Started May 21 12:54:17 PM PDT 24
Finished May 21 12:54:23 PM PDT 24
Peak memory 220516 kb
Host smart-b018c5b4-a1ee-4ad9-8b89-1562aafc1667
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614563790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.3614563790 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_alert_test/latest

Test location /workspace/coverage/default/16.kmac_app.641431296
Short name T490
Test name
Test status
Simulation time 48864119228 ps
CPU time 340.08 seconds
Started May 21 12:54:15 PM PDT 24
Finished May 21 12:59:59 PM PDT 24
Peak memory 248112 kb
Host smart-6717f18b-da50-4296-a19d-872be24e9fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641431296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.641431296 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_app/latest

Test location /workspace/coverage/default/16.kmac_burst_write.32277699
Short name T873
Test name
Test status
Simulation time 73949466936 ps
CPU time 784.48 seconds
Started May 21 12:54:04 PM PDT 24
Finished May 21 01:07:12 PM PDT 24
Peak memory 236504 kb
Host smart-2ad979d4-6e63-405f-a45a-843aa03bbc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32277699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.32277699 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_burst_write/latest

Test location /workspace/coverage/default/16.kmac_edn_timeout_error.1636409320
Short name T863
Test name
Test status
Simulation time 1245461886 ps
CPU time 37.27 seconds
Started May 21 12:54:04 PM PDT 24
Finished May 21 12:54:44 PM PDT 24
Peak memory 226592 kb
Host smart-30bec806-91cc-48a9-b25c-0894f72fee36
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1636409320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.1636409320 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_mode_error.1074045247
Short name T325
Test name
Test status
Simulation time 187105590 ps
CPU time 1.08 seconds
Started May 21 12:54:11 PM PDT 24
Finished May 21 12:54:15 PM PDT 24
Peak memory 221656 kb
Host smart-ed1b7a00-181d-4d57-b844-85d7bdd9a47b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1074045247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.1074045247 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_refresh.2678442461
Short name T775
Test name
Test status
Simulation time 565693438 ps
CPU time 10.03 seconds
Started May 21 12:54:16 PM PDT 24
Finished May 21 12:54:30 PM PDT 24
Peak memory 226672 kb
Host smart-c282b32b-200b-4933-879c-3b3c11add82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678442461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.2678442461 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/16.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/16.kmac_error.3549089356
Short name T347
Test name
Test status
Simulation time 4325679806 ps
CPU time 99.83 seconds
Started May 21 12:54:05 PM PDT 24
Finished May 21 12:55:49 PM PDT 24
Peak memory 240748 kb
Host smart-87c8f535-3108-4c22-be36-d232cda74cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549089356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.3549089356 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_error/latest

Test location /workspace/coverage/default/16.kmac_key_error.3384616555
Short name T834
Test name
Test status
Simulation time 985397843 ps
CPU time 8.94 seconds
Started May 21 12:54:14 PM PDT 24
Finished May 21 12:54:26 PM PDT 24
Peak memory 218460 kb
Host smart-0e0a438e-15e5-4c92-b08e-964786601e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384616555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.3384616555 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_key_error/latest

Test location /workspace/coverage/default/16.kmac_lc_escalation.586092881
Short name T702
Test name
Test status
Simulation time 46474153 ps
CPU time 1.27 seconds
Started May 21 12:54:05 PM PDT 24
Finished May 21 12:54:10 PM PDT 24
Peak memory 218648 kb
Host smart-ff04f5a7-e3ab-4988-a0c4-a13cb9334aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586092881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.586092881 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/16.kmac_lc_escalation/latest

Test location /workspace/coverage/default/16.kmac_long_msg_and_output.2690718706
Short name T210
Test name
Test status
Simulation time 27241880699 ps
CPU time 848.25 seconds
Started May 21 12:54:16 PM PDT 24
Finished May 21 01:08:29 PM PDT 24
Peak memory 296288 kb
Host smart-7c21774b-ab64-4f1b-9ece-7d842f8d8503
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690718706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_a
nd_output.2690718706 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/16.kmac_sideload.4099831577
Short name T584
Test name
Test status
Simulation time 17164965306 ps
CPU time 117.45 seconds
Started May 21 12:54:07 PM PDT 24
Finished May 21 12:56:07 PM PDT 24
Peak memory 230880 kb
Host smart-986cfc65-1e0e-4181-845f-33414c4545dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099831577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.4099831577 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_sideload/latest

Test location /workspace/coverage/default/16.kmac_smoke.2698155687
Short name T291
Test name
Test status
Simulation time 2995474728 ps
CPU time 28.18 seconds
Started May 21 12:54:01 PM PDT 24
Finished May 21 12:54:32 PM PDT 24
Peak memory 226704 kb
Host smart-5db063dc-845b-49a1-85a8-8174d1c28488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698155687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.2698155687 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_smoke/latest

Test location /workspace/coverage/default/16.kmac_stress_all.2348517331
Short name T725
Test name
Test status
Simulation time 18581800225 ps
CPU time 591.9 seconds
Started May 21 12:54:16 PM PDT 24
Finished May 21 01:04:12 PM PDT 24
Peak memory 289624 kb
Host smart-57c7b720-c0ad-4530-a3cb-d317830e9fee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2348517331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.2348517331 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_stress_all/latest

Test location /workspace/coverage/default/16.kmac_stress_all_with_rand_reset.3020856581
Short name T857
Test name
Test status
Simulation time 53318510193 ps
CPU time 177.4 seconds
Started May 21 12:54:16 PM PDT 24
Finished May 21 12:57:18 PM PDT 24
Peak memory 251208 kb
Host smart-f135516d-8ff1-4fa7-bcb8-19a975d9b3f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3020856581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all_with_rand_reset.3020856581 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac.1397554314
Short name T626
Test name
Test status
Simulation time 231274331 ps
CPU time 5.8 seconds
Started May 21 12:54:06 PM PDT 24
Finished May 21 12:54:16 PM PDT 24
Peak memory 218640 kb
Host smart-181598f1-7649-44f5-b191-46759cb69dc4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397554314 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.kmac_test_vectors_kmac.1397554314 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac_xof.3248055701
Short name T708
Test name
Test status
Simulation time 229280760 ps
CPU time 6.44 seconds
Started May 21 12:54:04 PM PDT 24
Finished May 21 12:54:14 PM PDT 24
Peak memory 218624 kb
Host smart-9aae0047-93d8-4942-89e5-9abb2f47e074
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248055701 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.kmac_test_vectors_kmac_xof.3248055701 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_224.2951423444
Short name T586
Test name
Test status
Simulation time 441830705488 ps
CPU time 2399.84 seconds
Started May 21 12:54:22 PM PDT 24
Finished May 21 01:34:26 PM PDT 24
Peak memory 391744 kb
Host smart-8d05adf5-7eaf-4330-b2e8-87e73b537065
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2951423444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_224.2951423444 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_256.488659927
Short name T925
Test name
Test status
Simulation time 123487347935 ps
CPU time 1936.76 seconds
Started May 21 12:54:06 PM PDT 24
Finished May 21 01:26:27 PM PDT 24
Peak memory 386484 kb
Host smart-9648a846-51b9-4347-99cc-3c7cdb5a6acd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=488659927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_256.488659927 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_384.2539680534
Short name T760
Test name
Test status
Simulation time 60144989121 ps
CPU time 1525.32 seconds
Started May 21 12:54:20 PM PDT 24
Finished May 21 01:19:50 PM PDT 24
Peak memory 332592 kb
Host smart-9339042d-a4a3-4591-92f8-8b5bc572eb94
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2539680534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_384.2539680534 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_512.1562136176
Short name T938
Test name
Test status
Simulation time 35757694264 ps
CPU time 1236.09 seconds
Started May 21 12:54:00 PM PDT 24
Finished May 21 01:14:38 PM PDT 24
Peak memory 305016 kb
Host smart-d8734620-1fb8-41ed-be9e-259ffc496a39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1562136176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_512.1562136176 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_shake_128.3674934056
Short name T1000
Test name
Test status
Simulation time 270782215165 ps
CPU time 5895.25 seconds
Started May 21 12:54:12 PM PDT 24
Finished May 21 02:32:31 PM PDT 24
Peak memory 657484 kb
Host smart-552bee4b-500b-450c-a992-d6b2c051d6ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3674934056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_128.3674934056 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_shake_256.2018924029
Short name T498
Test name
Test status
Simulation time 52637556266 ps
CPU time 4516.26 seconds
Started May 21 12:54:06 PM PDT 24
Finished May 21 02:09:27 PM PDT 24
Peak memory 583328 kb
Host smart-87fa7984-423d-4207-b3e6-0717c7634773
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2018924029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_256.2018924029 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/17.kmac_alert_test.3908728454
Short name T1062
Test name
Test status
Simulation time 48313645 ps
CPU time 0.84 seconds
Started May 21 12:54:14 PM PDT 24
Finished May 21 12:54:19 PM PDT 24
Peak memory 218424 kb
Host smart-e401f150-05b4-410b-aecb-a6671354f531
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908728454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.3908728454 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_alert_test/latest

Test location /workspace/coverage/default/17.kmac_app.3027423787
Short name T226
Test name
Test status
Simulation time 5632824297 ps
CPU time 148.28 seconds
Started May 21 12:54:23 PM PDT 24
Finished May 21 12:56:55 PM PDT 24
Peak memory 237320 kb
Host smart-eab92adf-aee3-4708-a04b-742c12bfc27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027423787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.3027423787 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_app/latest

Test location /workspace/coverage/default/17.kmac_burst_write.3789700203
Short name T1017
Test name
Test status
Simulation time 7301860977 ps
CPU time 293.87 seconds
Started May 21 12:54:19 PM PDT 24
Finished May 21 12:59:17 PM PDT 24
Peak memory 236008 kb
Host smart-d312cf8d-72f6-4f72-aea3-3100a796623a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789700203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.3789700203 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_burst_write/latest

Test location /workspace/coverage/default/17.kmac_edn_timeout_error.1030687678
Short name T820
Test name
Test status
Simulation time 1464389350 ps
CPU time 47.75 seconds
Started May 21 12:54:23 PM PDT 24
Finished May 21 12:55:14 PM PDT 24
Peak memory 227788 kb
Host smart-f7e006ee-8a80-4fc6-a26b-4f27ae8ee81f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1030687678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.1030687678 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_mode_error.173506457
Short name T579
Test name
Test status
Simulation time 27316195 ps
CPU time 1.03 seconds
Started May 21 12:54:19 PM PDT 24
Finished May 21 12:54:29 PM PDT 24
Peak memory 221608 kb
Host smart-1eca7877-196f-4cd7-a106-a33a544ddbee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=173506457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.173506457 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_refresh.2755941874
Short name T807
Test name
Test status
Simulation time 38852510272 ps
CPU time 208.91 seconds
Started May 21 12:54:07 PM PDT 24
Finished May 21 12:57:40 PM PDT 24
Peak memory 241772 kb
Host smart-5e1ed287-838d-4f07-89d9-9bf18d8037f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755941874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.2755941874 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/17.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/17.kmac_error.535496105
Short name T23
Test name
Test status
Simulation time 7456923505 ps
CPU time 178.04 seconds
Started May 21 12:54:19 PM PDT 24
Finished May 21 12:57:21 PM PDT 24
Peak memory 258220 kb
Host smart-2c802dbf-09f2-4633-92b4-0c5cfe463835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535496105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.535496105 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_error/latest

Test location /workspace/coverage/default/17.kmac_key_error.1123554161
Short name T4
Test name
Test status
Simulation time 2288469356 ps
CPU time 8.72 seconds
Started May 21 12:54:05 PM PDT 24
Finished May 21 12:54:18 PM PDT 24
Peak memory 218580 kb
Host smart-81f5c70f-ae86-4189-a858-a6d0ff572ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123554161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.1123554161 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_key_error/latest

Test location /workspace/coverage/default/17.kmac_lc_escalation.2091976158
Short name T48
Test name
Test status
Simulation time 102446567 ps
CPU time 1.23 seconds
Started May 21 12:54:13 PM PDT 24
Finished May 21 12:54:17 PM PDT 24
Peak memory 218652 kb
Host smart-00fafbc6-a118-42cf-81c2-7e52076d752c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091976158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.2091976158 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/17.kmac_lc_escalation/latest

Test location /workspace/coverage/default/17.kmac_long_msg_and_output.1809022078
Short name T1005
Test name
Test status
Simulation time 14933366378 ps
CPU time 1638.04 seconds
Started May 21 12:54:21 PM PDT 24
Finished May 21 01:21:43 PM PDT 24
Peak memory 363360 kb
Host smart-a1db070f-c218-48d8-b9ea-ab628ad6786c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809022078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_a
nd_output.1809022078 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/17.kmac_sideload.3116833028
Short name T641
Test name
Test status
Simulation time 48953503606 ps
CPU time 400.79 seconds
Started May 21 12:54:16 PM PDT 24
Finished May 21 01:01:01 PM PDT 24
Peak memory 248856 kb
Host smart-8bd9f42e-01c9-432a-acda-e748e32bf316
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116833028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.3116833028 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_sideload/latest

Test location /workspace/coverage/default/17.kmac_smoke.3240610613
Short name T362
Test name
Test status
Simulation time 3162386884 ps
CPU time 62.41 seconds
Started May 21 12:54:17 PM PDT 24
Finished May 21 12:55:24 PM PDT 24
Peak memory 221620 kb
Host smart-ca5cef24-c4c6-4511-a0ca-26b99d1d6a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240610613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.3240610613 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_smoke/latest

Test location /workspace/coverage/default/17.kmac_stress_all.2194432025
Short name T740
Test name
Test status
Simulation time 93223788878 ps
CPU time 1823.73 seconds
Started May 21 12:54:18 PM PDT 24
Finished May 21 01:24:46 PM PDT 24
Peak memory 341688 kb
Host smart-9a46aa0f-b8b6-4bfc-9320-6e2a48448b01
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2194432025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.2194432025 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_stress_all/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac.2038431347
Short name T871
Test name
Test status
Simulation time 309929917 ps
CPU time 5.41 seconds
Started May 21 12:54:06 PM PDT 24
Finished May 21 12:54:15 PM PDT 24
Peak memory 219620 kb
Host smart-10154a1f-4f9a-406b-a00f-f0400e92058f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038431347 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.kmac_test_vectors_kmac.2038431347 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac_xof.2892141210
Short name T211
Test name
Test status
Simulation time 574453040 ps
CPU time 6.94 seconds
Started May 21 12:54:07 PM PDT 24
Finished May 21 12:54:18 PM PDT 24
Peak memory 226600 kb
Host smart-a89e0721-29ad-4a38-8e88-5c20a48257b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892141210 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.kmac_test_vectors_kmac_xof.2892141210 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_224.2811807696
Short name T647
Test name
Test status
Simulation time 89062315821 ps
CPU time 2131.11 seconds
Started May 21 12:54:07 PM PDT 24
Finished May 21 01:29:42 PM PDT 24
Peak memory 395300 kb
Host smart-f7ff6934-0c52-4145-a96b-f98514897822
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2811807696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_224.2811807696 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_256.3678407095
Short name T561
Test name
Test status
Simulation time 161604476546 ps
CPU time 2049.28 seconds
Started May 21 12:54:23 PM PDT 24
Finished May 21 01:28:35 PM PDT 24
Peak memory 390924 kb
Host smart-e6c8d22f-1f33-40ed-9eb5-874aceb15f50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3678407095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_256.3678407095 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_384.3189090499
Short name T391
Test name
Test status
Simulation time 14568584901 ps
CPU time 1412.13 seconds
Started May 21 12:54:18 PM PDT 24
Finished May 21 01:17:55 PM PDT 24
Peak memory 335660 kb
Host smart-e47d4afd-bbb0-4ea8-aeff-5d8220309d8e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3189090499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_384.3189090499 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_512.2459487659
Short name T360
Test name
Test status
Simulation time 99700309197 ps
CPU time 1311.52 seconds
Started May 21 12:54:12 PM PDT 24
Finished May 21 01:16:07 PM PDT 24
Peak memory 299476 kb
Host smart-b325ee42-4dc1-47e7-92ca-a4fd77071839
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2459487659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_512.2459487659 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_shake_128.3036488808
Short name T228
Test name
Test status
Simulation time 211422421713 ps
CPU time 4859.23 seconds
Started May 21 12:54:16 PM PDT 24
Finished May 21 02:15:21 PM PDT 24
Peak memory 636652 kb
Host smart-a8c12474-70c4-4fb9-893b-b2c62d908b30
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3036488808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_128.3036488808 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_shake_256.4288820356
Short name T516
Test name
Test status
Simulation time 1354162629539 ps
CPU time 4547.95 seconds
Started May 21 12:54:15 PM PDT 24
Finished May 21 02:10:08 PM PDT 24
Peak memory 567932 kb
Host smart-def9eabc-6906-4a75-9b93-0e4b1add0f05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4288820356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_256.4288820356 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/18.kmac_alert_test.2129470518
Short name T374
Test name
Test status
Simulation time 16944954 ps
CPU time 0.82 seconds
Started May 21 12:54:16 PM PDT 24
Finished May 21 12:54:22 PM PDT 24
Peak memory 218520 kb
Host smart-10cb0355-5aba-4411-91af-7cab947ccae0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129470518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.2129470518 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_alert_test/latest

Test location /workspace/coverage/default/18.kmac_app.48917668
Short name T794
Test name
Test status
Simulation time 2563559701 ps
CPU time 59.31 seconds
Started May 21 12:54:17 PM PDT 24
Finished May 21 12:55:21 PM PDT 24
Peak memory 228348 kb
Host smart-5af875f1-2cbe-4fac-900c-1b7c535b9950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48917668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.48917668 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_app/latest

Test location /workspace/coverage/default/18.kmac_burst_write.3884083435
Short name T92
Test name
Test status
Simulation time 21242998218 ps
CPU time 543.73 seconds
Started May 21 12:54:12 PM PDT 24
Finished May 21 01:03:19 PM PDT 24
Peak memory 233668 kb
Host smart-008add51-db5d-49d8-8c83-6f037ac951ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884083435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.3884083435 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_burst_write/latest

Test location /workspace/coverage/default/18.kmac_edn_timeout_error.4223729314
Short name T803
Test name
Test status
Simulation time 38748199 ps
CPU time 1.21 seconds
Started May 21 12:54:15 PM PDT 24
Finished May 21 12:54:21 PM PDT 24
Peak memory 218536 kb
Host smart-b8a98aca-dea2-4615-83a6-5d76cd9b70ca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4223729314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.4223729314 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_mode_error.2311036968
Short name T998
Test name
Test status
Simulation time 81459505 ps
CPU time 1.2 seconds
Started May 21 12:54:29 PM PDT 24
Finished May 21 12:54:33 PM PDT 24
Peak memory 222116 kb
Host smart-2e676947-8e59-4906-8ccf-95fc8607bb74
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2311036968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.2311036968 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_refresh.848456051
Short name T722
Test name
Test status
Simulation time 5815801819 ps
CPU time 185.46 seconds
Started May 21 12:54:13 PM PDT 24
Finished May 21 12:57:21 PM PDT 24
Peak memory 241276 kb
Host smart-d1711894-b4db-4b68-881b-4ece3ba2105e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848456051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.848456051 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/18.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/18.kmac_key_error.553921839
Short name T522
Test name
Test status
Simulation time 1084661520 ps
CPU time 8.14 seconds
Started May 21 12:54:18 PM PDT 24
Finished May 21 12:54:31 PM PDT 24
Peak memory 218556 kb
Host smart-a90869ef-b873-4320-b083-499d65338324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553921839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.553921839 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_key_error/latest

Test location /workspace/coverage/default/18.kmac_lc_escalation.1780900462
Short name T79
Test name
Test status
Simulation time 65719430 ps
CPU time 1.37 seconds
Started May 21 12:54:17 PM PDT 24
Finished May 21 12:54:24 PM PDT 24
Peak memory 219524 kb
Host smart-6e48f732-d03c-4d40-a4bf-93a9ad9292e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780900462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.1780900462 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/18.kmac_lc_escalation/latest

Test location /workspace/coverage/default/18.kmac_long_msg_and_output.2600180305
Short name T838
Test name
Test status
Simulation time 7666408011 ps
CPU time 322.83 seconds
Started May 21 12:54:16 PM PDT 24
Finished May 21 12:59:44 PM PDT 24
Peak memory 247808 kb
Host smart-6ddee22f-4fc8-42b8-8959-4c8dc1caafde
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600180305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_a
nd_output.2600180305 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/18.kmac_sideload.1343028218
Short name T168
Test name
Test status
Simulation time 36027437849 ps
CPU time 258.04 seconds
Started May 21 12:54:20 PM PDT 24
Finished May 21 12:58:42 PM PDT 24
Peak memory 241560 kb
Host smart-de707921-58ea-4331-acbb-33de6cc75d8a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343028218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.1343028218 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_sideload/latest

Test location /workspace/coverage/default/18.kmac_smoke.3871496522
Short name T545
Test name
Test status
Simulation time 1680290209 ps
CPU time 66.17 seconds
Started May 21 12:54:34 PM PDT 24
Finished May 21 12:55:41 PM PDT 24
Peak memory 218640 kb
Host smart-0ccf052c-caac-4161-b1f8-2d9a9b99e804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871496522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.3871496522 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_smoke/latest

Test location /workspace/coverage/default/18.kmac_stress_all.4167594412
Short name T346
Test name
Test status
Simulation time 191247854660 ps
CPU time 1380.88 seconds
Started May 21 12:54:17 PM PDT 24
Finished May 21 01:17:23 PM PDT 24
Peak memory 335088 kb
Host smart-1a52b6bc-e763-4b23-9fa9-9e9a199c3fcc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4167594412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.4167594412 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_stress_all/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac.649244329
Short name T273
Test name
Test status
Simulation time 417238265 ps
CPU time 5.32 seconds
Started May 21 12:54:15 PM PDT 24
Finished May 21 12:54:25 PM PDT 24
Peak memory 226636 kb
Host smart-c626ef6f-a2c3-4bc5-9a05-e191102212cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649244329 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.kmac_test_vectors_kmac.649244329 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac_xof.3847529202
Short name T393
Test name
Test status
Simulation time 120948426 ps
CPU time 5.56 seconds
Started May 21 12:54:11 PM PDT 24
Finished May 21 12:54:20 PM PDT 24
Peak memory 218576 kb
Host smart-ae7c9d9a-e011-4a4e-a020-cd2ff072f188
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847529202 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.kmac_test_vectors_kmac_xof.3847529202 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_224.3591242776
Short name T1034
Test name
Test status
Simulation time 65196455307 ps
CPU time 2190.76 seconds
Started May 21 12:54:18 PM PDT 24
Finished May 21 01:30:54 PM PDT 24
Peak memory 394992 kb
Host smart-b3f5f361-6f28-44b5-982c-3e4bf204b59a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3591242776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_224.3591242776 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_256.1197165234
Short name T177
Test name
Test status
Simulation time 90884703937 ps
CPU time 2258.32 seconds
Started May 21 12:54:19 PM PDT 24
Finished May 21 01:32:02 PM PDT 24
Peak memory 383940 kb
Host smart-ca352251-d529-47e0-b71e-0e7dd07c7620
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1197165234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_256.1197165234 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_384.3366763526
Short name T521
Test name
Test status
Simulation time 72820754630 ps
CPU time 1802.77 seconds
Started May 21 12:54:13 PM PDT 24
Finished May 21 01:24:19 PM PDT 24
Peak memory 343220 kb
Host smart-8477914b-9b3e-464a-be55-fc77205fb272
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3366763526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_384.3366763526 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_512.731367432
Short name T248
Test name
Test status
Simulation time 50598699667 ps
CPU time 1251.33 seconds
Started May 21 12:54:14 PM PDT 24
Finished May 21 01:15:09 PM PDT 24
Peak memory 301392 kb
Host smart-400e9a47-a28f-4c2f-94b9-8d0987d99dcd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=731367432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_512.731367432 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_128.599955636
Short name T178
Test name
Test status
Simulation time 247297460403 ps
CPU time 5091.26 seconds
Started May 21 12:54:12 PM PDT 24
Finished May 21 02:19:07 PM PDT 24
Peak memory 647384 kb
Host smart-435f0de9-785f-4e3d-94ed-16d3c4348375
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=599955636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_128.599955636 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_256.1793464959
Short name T463
Test name
Test status
Simulation time 165767567984 ps
CPU time 4534.18 seconds
Started May 21 12:54:14 PM PDT 24
Finished May 21 02:09:51 PM PDT 24
Peak memory 582976 kb
Host smart-0c431eaa-bd9f-41b7-8e6c-6245e6bd71b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1793464959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_256.1793464959 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/19.kmac_alert_test.3328543576
Short name T470
Test name
Test status
Simulation time 12693733 ps
CPU time 0.83 seconds
Started May 21 12:54:24 PM PDT 24
Finished May 21 12:54:28 PM PDT 24
Peak memory 220520 kb
Host smart-72649ee8-5faf-425d-bbbf-16de98008665
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328543576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.3328543576 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_alert_test/latest

Test location /workspace/coverage/default/19.kmac_app.3578487788
Short name T825
Test name
Test status
Simulation time 2339221834 ps
CPU time 124.1 seconds
Started May 21 12:54:23 PM PDT 24
Finished May 21 12:56:30 PM PDT 24
Peak memory 236104 kb
Host smart-96229010-fe1f-4c69-86c6-bc09172e46c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578487788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.3578487788 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_app/latest

Test location /workspace/coverage/default/19.kmac_burst_write.2876712118
Short name T573
Test name
Test status
Simulation time 38899572793 ps
CPU time 1139.52 seconds
Started May 21 12:54:17 PM PDT 24
Finished May 21 01:13:21 PM PDT 24
Peak memory 238624 kb
Host smart-f4e4bf29-657f-4218-bf78-fe0876e89f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876712118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.2876712118 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_burst_write/latest

Test location /workspace/coverage/default/19.kmac_edn_timeout_error.1731025982
Short name T892
Test name
Test status
Simulation time 29145815 ps
CPU time 0.94 seconds
Started May 21 12:54:31 PM PDT 24
Finished May 21 12:54:33 PM PDT 24
Peak memory 218384 kb
Host smart-df1556f3-f0d2-432d-9e56-fef99590c960
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1731025982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.1731025982 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_mode_error.2938762800
Short name T310
Test name
Test status
Simulation time 95912903 ps
CPU time 0.87 seconds
Started May 21 12:54:24 PM PDT 24
Finished May 21 12:54:28 PM PDT 24
Peak memory 220368 kb
Host smart-20d372ca-a4cd-4e59-ae95-3012de78368c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2938762800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.2938762800 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_refresh.4082161992
Short name T931
Test name
Test status
Simulation time 10620643327 ps
CPU time 86.7 seconds
Started May 21 12:54:29 PM PDT 24
Finished May 21 12:55:58 PM PDT 24
Peak memory 232876 kb
Host smart-47ab47c1-b4ba-47b4-b811-8fc1473c62d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082161992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.4082161992 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/19.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/19.kmac_error.3807802442
Short name T42
Test name
Test status
Simulation time 40675223811 ps
CPU time 238.2 seconds
Started May 21 12:54:24 PM PDT 24
Finished May 21 12:58:25 PM PDT 24
Peak memory 252576 kb
Host smart-a1e19001-de9e-4563-b3e8-82e9efdf1300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807802442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.3807802442 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_error/latest

Test location /workspace/coverage/default/19.kmac_key_error.1381414433
Short name T993
Test name
Test status
Simulation time 5137541896 ps
CPU time 12.64 seconds
Started May 21 12:54:29 PM PDT 24
Finished May 21 12:54:44 PM PDT 24
Peak memory 218536 kb
Host smart-3136f803-32d8-47ae-82f3-b19bcf0ccfaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381414433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.1381414433 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_key_error/latest

Test location /workspace/coverage/default/19.kmac_lc_escalation.1431823904
Short name T909
Test name
Test status
Simulation time 80196054 ps
CPU time 1.41 seconds
Started May 21 12:54:29 PM PDT 24
Finished May 21 12:54:32 PM PDT 24
Peak memory 218640 kb
Host smart-c0e55fed-4a8a-46c3-a9f3-3b6a22b631cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431823904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.1431823904 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/19.kmac_lc_escalation/latest

Test location /workspace/coverage/default/19.kmac_long_msg_and_output.1490036420
Short name T847
Test name
Test status
Simulation time 60379759601 ps
CPU time 2132.36 seconds
Started May 21 12:54:20 PM PDT 24
Finished May 21 01:29:56 PM PDT 24
Peak memory 394816 kb
Host smart-1db7b171-2398-4532-b546-d506e47ecea0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490036420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_a
nd_output.1490036420 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/19.kmac_sideload.860070799
Short name T801
Test name
Test status
Simulation time 7384944901 ps
CPU time 381.2 seconds
Started May 21 12:54:21 PM PDT 24
Finished May 21 01:00:46 PM PDT 24
Peak memory 250208 kb
Host smart-852f59c2-e411-4a24-984c-beaba152a155
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860070799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.860070799 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_sideload/latest

Test location /workspace/coverage/default/19.kmac_smoke.3066826933
Short name T569
Test name
Test status
Simulation time 747714205 ps
CPU time 18.63 seconds
Started May 21 12:54:21 PM PDT 24
Finished May 21 12:54:43 PM PDT 24
Peak memory 218964 kb
Host smart-f2e6e5a0-5ecc-44c1-a8f8-058c665faee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066826933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.3066826933 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_smoke/latest

Test location /workspace/coverage/default/19.kmac_stress_all.2873493488
Short name T240
Test name
Test status
Simulation time 72898148627 ps
CPU time 962.8 seconds
Started May 21 12:54:24 PM PDT 24
Finished May 21 01:10:30 PM PDT 24
Peak memory 319188 kb
Host smart-c4165b56-10b6-4147-93e5-2ba8e88304ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2873493488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.2873493488 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_stress_all/latest

Test location /workspace/coverage/default/19.kmac_stress_all_with_rand_reset.3058083657
Short name T1032
Test name
Test status
Simulation time 83214983281 ps
CPU time 2219.87 seconds
Started May 21 12:54:27 PM PDT 24
Finished May 21 01:31:29 PM PDT 24
Peak memory 348924 kb
Host smart-0e64d709-c93e-4a39-98de-9d577b951279
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3058083657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all_with_rand_reset.3058083657 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac.3236253134
Short name T294
Test name
Test status
Simulation time 560172689 ps
CPU time 6.52 seconds
Started May 21 12:54:16 PM PDT 24
Finished May 21 12:54:27 PM PDT 24
Peak memory 226696 kb
Host smart-ed9c4be9-8090-489b-912b-53b954cd74d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236253134 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.kmac_test_vectors_kmac.3236253134 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac_xof.3858122087
Short name T512
Test name
Test status
Simulation time 1838732316 ps
CPU time 7.24 seconds
Started May 21 12:54:20 PM PDT 24
Finished May 21 12:54:31 PM PDT 24
Peak memory 226708 kb
Host smart-a0bf0de9-598d-4efe-bced-7c898a836c96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858122087 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.kmac_test_vectors_kmac_xof.3858122087 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_224.2788619253
Short name T558
Test name
Test status
Simulation time 53211996649 ps
CPU time 2046.81 seconds
Started May 21 12:54:21 PM PDT 24
Finished May 21 01:28:32 PM PDT 24
Peak memory 390000 kb
Host smart-bb63ac2b-4b3e-4ee2-bfe7-5c7356f43bac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2788619253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_224.2788619253 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_256.4193205955
Short name T239
Test name
Test status
Simulation time 164615039933 ps
CPU time 2208.8 seconds
Started May 21 12:54:28 PM PDT 24
Finished May 21 01:31:19 PM PDT 24
Peak memory 381656 kb
Host smart-1977b9d7-3792-441a-8dda-e3e372163c20
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4193205955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_256.4193205955 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_384.20123568
Short name T1015
Test name
Test status
Simulation time 506708841015 ps
CPU time 1878.36 seconds
Started May 21 12:54:19 PM PDT 24
Finished May 21 01:25:42 PM PDT 24
Peak memory 341540 kb
Host smart-3bc07841-5c5a-42ef-ae8d-5e6c23454d9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=20123568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_384.20123568 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_512.4213100272
Short name T718
Test name
Test status
Simulation time 43699620345 ps
CPU time 1092.32 seconds
Started May 21 12:54:21 PM PDT 24
Finished May 21 01:12:37 PM PDT 24
Peak memory 301176 kb
Host smart-f70caced-3739-414b-a056-e53bc11c49b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4213100272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_512.4213100272 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_128.3314122991
Short name T969
Test name
Test status
Simulation time 118676825684 ps
CPU time 4907.89 seconds
Started May 21 12:54:17 PM PDT 24
Finished May 21 02:16:10 PM PDT 24
Peak memory 648800 kb
Host smart-d7d4d330-7bae-45c3-a4ad-eed87730135e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3314122991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_128.3314122991 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_256.2502960405
Short name T359
Test name
Test status
Simulation time 208584412409 ps
CPU time 4427.32 seconds
Started May 21 12:54:21 PM PDT 24
Finished May 21 02:08:12 PM PDT 24
Peak memory 567664 kb
Host smart-6fd8dad7-3311-48d9-887c-5c56993f3e8a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2502960405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_256.2502960405 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/2.kmac_alert_test.552104551
Short name T858
Test name
Test status
Simulation time 27958967 ps
CPU time 0.82 seconds
Started May 21 12:53:21 PM PDT 24
Finished May 21 12:53:26 PM PDT 24
Peak memory 218516 kb
Host smart-ca232113-02ce-4020-be4e-6fccfd11da98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552104551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.552104551 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/2.kmac_alert_test/latest

Test location /workspace/coverage/default/2.kmac_app.3419678714
Short name T861
Test name
Test status
Simulation time 23616936152 ps
CPU time 230.94 seconds
Started May 21 12:53:29 PM PDT 24
Finished May 21 12:57:23 PM PDT 24
Peak memory 244264 kb
Host smart-df5a0251-dbf0-4507-9eb0-3e3d3e960bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419678714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.3419678714 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_app/latest

Test location /workspace/coverage/default/2.kmac_app_with_partial_data.2416965652
Short name T768
Test name
Test status
Simulation time 22713492698 ps
CPU time 39.71 seconds
Started May 21 12:53:32 PM PDT 24
Finished May 21 12:54:15 PM PDT 24
Peak memory 227004 kb
Host smart-afbf0cf3-5fb1-4f84-b00f-80a130c1cf54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416965652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.2416965652 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/2.kmac_burst_write.941056534
Short name T389
Test name
Test status
Simulation time 2276067794 ps
CPU time 59.58 seconds
Started May 21 12:53:38 PM PDT 24
Finished May 21 12:54:40 PM PDT 24
Peak memory 234948 kb
Host smart-4bae1aba-1c9f-4493-ac35-f65ae49332ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941056534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.941056534 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_burst_write/latest

Test location /workspace/coverage/default/2.kmac_edn_timeout_error.1324611375
Short name T578
Test name
Test status
Simulation time 1215403633 ps
CPU time 35.42 seconds
Started May 21 12:53:39 PM PDT 24
Finished May 21 12:54:16 PM PDT 24
Peak memory 226696 kb
Host smart-b26301ff-98d3-4622-8f10-ac10edd7a1db
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1324611375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.1324611375 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_mode_error.315391494
Short name T74
Test name
Test status
Simulation time 28327973 ps
CPU time 1 seconds
Started May 21 12:53:29 PM PDT 24
Finished May 21 12:53:34 PM PDT 24
Peak memory 222112 kb
Host smart-aa66ae6f-053d-4028-9e3a-020a49f6f3bd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=315391494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.315391494 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_ready_error.1383761396
Short name T12
Test name
Test status
Simulation time 11226447024 ps
CPU time 57.13 seconds
Started May 21 12:53:24 PM PDT 24
Finished May 21 12:54:25 PM PDT 24
Peak memory 226716 kb
Host smart-e7e681a5-3443-4c3b-9ae2-a2c1fae492ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383761396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.1383761396 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/2.kmac_error.2394302808
Short name T835
Test name
Test status
Simulation time 659964952 ps
CPU time 51.39 seconds
Started May 21 12:53:23 PM PDT 24
Finished May 21 12:54:19 PM PDT 24
Peak memory 235584 kb
Host smart-7048f626-96e4-4f6b-b3fc-98b749c4764f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394302808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.2394302808 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_error/latest

Test location /workspace/coverage/default/2.kmac_key_error.1987948836
Short name T234
Test name
Test status
Simulation time 14562221775 ps
CPU time 11.78 seconds
Started May 21 12:53:47 PM PDT 24
Finished May 21 12:54:03 PM PDT 24
Peak memory 218560 kb
Host smart-fd8469bf-f458-493e-92bc-2577845918dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987948836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.1987948836 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_key_error/latest

Test location /workspace/coverage/default/2.kmac_lc_escalation.153053126
Short name T29
Test name
Test status
Simulation time 110693863 ps
CPU time 4.18 seconds
Started May 21 12:53:25 PM PDT 24
Finished May 21 12:53:33 PM PDT 24
Peak memory 221532 kb
Host smart-18b12ea0-ad99-4188-a3a7-bf532be87cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153053126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.153053126 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_lc_escalation/latest

Test location /workspace/coverage/default/2.kmac_long_msg_and_output.2362111308
Short name T138
Test name
Test status
Simulation time 7679191701 ps
CPU time 251.7 seconds
Started May 21 12:53:33 PM PDT 24
Finished May 21 12:57:48 PM PDT 24
Peak memory 243948 kb
Host smart-18a6cb1a-6b34-470f-97b7-ef57781822c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362111308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_an
d_output.2362111308 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/2.kmac_mubi.3934858217
Short name T430
Test name
Test status
Simulation time 29107665288 ps
CPU time 59.31 seconds
Started May 21 12:53:25 PM PDT 24
Finished May 21 12:54:28 PM PDT 24
Peak memory 227284 kb
Host smart-308069bb-c317-42d8-802f-05aae6fbc795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934858217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.3934858217 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mubi/latest

Test location /workspace/coverage/default/2.kmac_sec_cm.4228929997
Short name T30
Test name
Test status
Simulation time 7292826599 ps
CPU time 46.24 seconds
Started May 21 12:53:53 PM PDT 24
Finished May 21 12:54:44 PM PDT 24
Peak memory 261272 kb
Host smart-47c2082d-565f-4e6c-8054-85e2d86a8f5c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228929997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.4228929997 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/2.kmac_sec_cm/latest

Test location /workspace/coverage/default/2.kmac_sideload.4073773859
Short name T678
Test name
Test status
Simulation time 3300942926 ps
CPU time 138.42 seconds
Started May 21 12:53:27 PM PDT 24
Finished May 21 12:55:49 PM PDT 24
Peak memory 235084 kb
Host smart-d19e0b72-845f-4d8b-ac16-9346589d8e1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073773859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.4073773859 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_sideload/latest

Test location /workspace/coverage/default/2.kmac_smoke.3635368596
Short name T592
Test name
Test status
Simulation time 2385271202 ps
CPU time 74.65 seconds
Started May 21 12:53:35 PM PDT 24
Finished May 21 12:54:52 PM PDT 24
Peak memory 226772 kb
Host smart-5a053f1c-b825-4033-94e2-b027226e3a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635368596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.3635368596 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_smoke/latest

Test location /workspace/coverage/default/2.kmac_stress_all.2244057235
Short name T107
Test name
Test status
Simulation time 67749376627 ps
CPU time 868.85 seconds
Started May 21 12:53:30 PM PDT 24
Finished May 21 01:08:02 PM PDT 24
Peak memory 322540 kb
Host smart-d411136b-6ac5-48d0-ad83-dc8699b0cef9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2244057235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.2244057235 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_stress_all/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac.2932104830
Short name T620
Test name
Test status
Simulation time 411728340 ps
CPU time 6.16 seconds
Started May 21 12:53:29 PM PDT 24
Finished May 21 12:53:39 PM PDT 24
Peak memory 219568 kb
Host smart-477566e1-aa1b-48cd-8c93-1a11e6921bf7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932104830 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.kmac_test_vectors_kmac.2932104830 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac_xof.1601800906
Short name T707
Test name
Test status
Simulation time 784801475 ps
CPU time 6.09 seconds
Started May 21 12:53:27 PM PDT 24
Finished May 21 12:53:36 PM PDT 24
Peak memory 226328 kb
Host smart-17bf955f-37a9-418c-bd40-d93454fec1b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601800906 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.kmac_test_vectors_kmac_xof.1601800906 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_224.653580620
Short name T1063
Test name
Test status
Simulation time 392187598464 ps
CPU time 2497.2 seconds
Started May 21 12:53:49 PM PDT 24
Finished May 21 01:35:30 PM PDT 24
Peak memory 396832 kb
Host smart-a456a6e3-4c95-4bf4-98e7-77dcfa7cb54e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=653580620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.653580620 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_256.1052345745
Short name T929
Test name
Test status
Simulation time 388104075775 ps
CPU time 2337.06 seconds
Started May 21 12:53:39 PM PDT 24
Finished May 21 01:32:38 PM PDT 24
Peak memory 391976 kb
Host smart-d0a9d14a-9238-49d9-b69b-e7629cb864b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1052345745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.1052345745 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_384.826609912
Short name T836
Test name
Test status
Simulation time 195288538676 ps
CPU time 1781.39 seconds
Started May 21 12:53:22 PM PDT 24
Finished May 21 01:23:09 PM PDT 24
Peak memory 347748 kb
Host smart-4de391b1-099b-4714-a7d8-db8c0e387751
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=826609912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.826609912 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_512.1815505387
Short name T1025
Test name
Test status
Simulation time 34866238749 ps
CPU time 1306.06 seconds
Started May 21 12:53:22 PM PDT 24
Finished May 21 01:15:13 PM PDT 24
Peak memory 300752 kb
Host smart-8f85b62e-b9a8-41db-8e28-dd459c69d747
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1815505387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.1815505387 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_128.969698013
Short name T302
Test name
Test status
Simulation time 1268230097372 ps
CPU time 6374.39 seconds
Started May 21 12:53:44 PM PDT 24
Finished May 21 02:40:02 PM PDT 24
Peak memory 656204 kb
Host smart-f5cfcbc2-9cb6-486e-bd8a-5f9c9ea8c62a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=969698013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.969698013 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_256.1170219249
Short name T235
Test name
Test status
Simulation time 495440341983 ps
CPU time 4499.27 seconds
Started May 21 12:53:22 PM PDT 24
Finished May 21 02:08:27 PM PDT 24
Peak memory 566600 kb
Host smart-1163e669-c633-486c-a2bf-a722fc2d15a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1170219249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.1170219249 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/20.kmac_alert_test.774056612
Short name T348
Test name
Test status
Simulation time 23157803 ps
CPU time 0.79 seconds
Started May 21 12:54:34 PM PDT 24
Finished May 21 12:54:36 PM PDT 24
Peak memory 218516 kb
Host smart-6fe60b01-470a-4ade-8a39-a974ec8f6e8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774056612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.774056612 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/20.kmac_alert_test/latest

Test location /workspace/coverage/default/20.kmac_app.174469164
Short name T1064
Test name
Test status
Simulation time 10674484654 ps
CPU time 81.16 seconds
Started May 21 12:54:25 PM PDT 24
Finished May 21 12:55:49 PM PDT 24
Peak memory 230644 kb
Host smart-d9d4e8a9-4d0e-4ce5-b06a-6b3dedf5d9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174469164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.174469164 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_app/latest

Test location /workspace/coverage/default/20.kmac_burst_write.2078406550
Short name T610
Test name
Test status
Simulation time 20089737439 ps
CPU time 898.67 seconds
Started May 21 12:54:23 PM PDT 24
Finished May 21 01:09:25 PM PDT 24
Peak memory 237528 kb
Host smart-e3d0a250-2968-42e0-9608-ed882c006de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078406550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.2078406550 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_burst_write/latest

Test location /workspace/coverage/default/20.kmac_entropy_refresh.2476426035
Short name T1014
Test name
Test status
Simulation time 872001199 ps
CPU time 6.37 seconds
Started May 21 12:54:30 PM PDT 24
Finished May 21 12:54:38 PM PDT 24
Peak memory 226632 kb
Host smart-fd2dbb14-bf1a-4ffa-a901-e1344d2665b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476426035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.2476426035 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/20.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/20.kmac_error.3771995767
Short name T615
Test name
Test status
Simulation time 3006874783 ps
CPU time 141.77 seconds
Started May 21 12:54:38 PM PDT 24
Finished May 21 12:57:01 PM PDT 24
Peak memory 251756 kb
Host smart-0ca79483-c07a-4387-b69d-c0a0315ee67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771995767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.3771995767 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_error/latest

Test location /workspace/coverage/default/20.kmac_lc_escalation.3618072890
Short name T1030
Test name
Test status
Simulation time 68233594 ps
CPU time 1.45 seconds
Started May 21 12:54:29 PM PDT 24
Finished May 21 12:54:33 PM PDT 24
Peak memory 219556 kb
Host smart-308c4cde-befa-486c-8125-37bb70978908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618072890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.3618072890 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/20.kmac_lc_escalation/latest

Test location /workspace/coverage/default/20.kmac_long_msg_and_output.346671015
Short name T188
Test name
Test status
Simulation time 13783415189 ps
CPU time 475.94 seconds
Started May 21 12:54:38 PM PDT 24
Finished May 21 01:02:35 PM PDT 24
Peak memory 261472 kb
Host smart-b5c1aa2b-5e11-4b13-8542-97d1a0692393
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346671015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_an
d_output.346671015 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/20.kmac_sideload.4116862864
Short name T145
Test name
Test status
Simulation time 7857065291 ps
CPU time 288.66 seconds
Started May 21 12:54:25 PM PDT 24
Finished May 21 12:59:16 PM PDT 24
Peak memory 246536 kb
Host smart-a470ad67-cb37-4e19-a37b-1fa86cbdb70f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116862864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.4116862864 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_sideload/latest

Test location /workspace/coverage/default/20.kmac_smoke.4188964994
Short name T1028
Test name
Test status
Simulation time 3494098113 ps
CPU time 75.58 seconds
Started May 21 12:54:23 PM PDT 24
Finished May 21 12:55:42 PM PDT 24
Peak memory 226764 kb
Host smart-7fa9dc36-cc28-4d38-83ee-90d7a4a2fc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188964994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.4188964994 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_smoke/latest

Test location /workspace/coverage/default/20.kmac_stress_all.919438345
Short name T363
Test name
Test status
Simulation time 12698820123 ps
CPU time 752.79 seconds
Started May 21 12:54:30 PM PDT 24
Finished May 21 01:07:05 PM PDT 24
Peak memory 303148 kb
Host smart-21bbbf83-1683-45e3-929f-17b652945eb5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=919438345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.919438345 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_stress_all/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac.186981626
Short name T308
Test name
Test status
Simulation time 1845954658 ps
CPU time 6.58 seconds
Started May 21 12:54:39 PM PDT 24
Finished May 21 12:54:47 PM PDT 24
Peak memory 226684 kb
Host smart-65bff4a1-f160-494c-a9ec-97637be9f253
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186981626 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.kmac_test_vectors_kmac.186981626 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac_xof.1783389504
Short name T281
Test name
Test status
Simulation time 1506665521 ps
CPU time 6.05 seconds
Started May 21 12:54:37 PM PDT 24
Finished May 21 12:54:45 PM PDT 24
Peak memory 218648 kb
Host smart-3ad5d37c-7fbe-4f57-9344-fe597a002834
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783389504 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.kmac_test_vectors_kmac_xof.1783389504 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_224.1108213552
Short name T833
Test name
Test status
Simulation time 21368282893 ps
CPU time 2076.83 seconds
Started May 21 12:54:26 PM PDT 24
Finished May 21 01:29:05 PM PDT 24
Peak memory 399308 kb
Host smart-53a9f868-87b6-4000-be75-3eced0836f6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1108213552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_224.1108213552 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_256.1931241002
Short name T396
Test name
Test status
Simulation time 65876559225 ps
CPU time 2104.15 seconds
Started May 21 12:54:34 PM PDT 24
Finished May 21 01:29:39 PM PDT 24
Peak memory 388080 kb
Host smart-1584e5db-ab67-42cd-adec-8fa0c7abde42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1931241002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_256.1931241002 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_384.1788718452
Short name T590
Test name
Test status
Simulation time 64568586571 ps
CPU time 1613.92 seconds
Started May 21 12:54:35 PM PDT 24
Finished May 21 01:21:29 PM PDT 24
Peak memory 338328 kb
Host smart-33727229-7efb-4951-9052-3b139804ddc8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1788718452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_384.1788718452 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_512.2009575443
Short name T870
Test name
Test status
Simulation time 420281043727 ps
CPU time 1289.34 seconds
Started May 21 12:54:29 PM PDT 24
Finished May 21 01:16:01 PM PDT 24
Peak memory 305864 kb
Host smart-c24d17e2-3585-4f89-a764-619e232da6fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2009575443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_512.2009575443 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_128.3951741761
Short name T855
Test name
Test status
Simulation time 257131648187 ps
CPU time 5889.92 seconds
Started May 21 12:54:30 PM PDT 24
Finished May 21 02:32:42 PM PDT 24
Peak memory 653048 kb
Host smart-e4228c54-5df4-46a1-b2fd-2a958aeed955
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3951741761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_128.3951741761 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_256.1014859040
Short name T283
Test name
Test status
Simulation time 146571479796 ps
CPU time 4579.66 seconds
Started May 21 12:54:29 PM PDT 24
Finished May 21 02:10:52 PM PDT 24
Peak memory 579268 kb
Host smart-95a73aea-3769-42e0-871d-a87fde1594e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1014859040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_256.1014859040 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/21.kmac_alert_test.3475084412
Short name T436
Test name
Test status
Simulation time 22303353 ps
CPU time 0.84 seconds
Started May 21 12:54:45 PM PDT 24
Finished May 21 12:54:47 PM PDT 24
Peak memory 218520 kb
Host smart-a3e7384b-3991-41c7-8b02-1c7777662d05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475084412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.3475084412 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_alert_test/latest

Test location /workspace/coverage/default/21.kmac_app.3652985432
Short name T968
Test name
Test status
Simulation time 89253528438 ps
CPU time 280.13 seconds
Started May 21 12:54:36 PM PDT 24
Finished May 21 12:59:17 PM PDT 24
Peak memory 246636 kb
Host smart-bad4fe1b-f630-47c5-bdc6-86b339dae40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652985432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.3652985432 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_app/latest

Test location /workspace/coverage/default/21.kmac_burst_write.2109170036
Short name T220
Test name
Test status
Simulation time 57631142308 ps
CPU time 1452.19 seconds
Started May 21 12:54:29 PM PDT 24
Finished May 21 01:18:43 PM PDT 24
Peak memory 238284 kb
Host smart-95f7967a-f407-481b-9f30-05b30600526c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109170036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.2109170036 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_burst_write/latest

Test location /workspace/coverage/default/21.kmac_entropy_refresh.377876550
Short name T616
Test name
Test status
Simulation time 10515070992 ps
CPU time 71.96 seconds
Started May 21 12:54:39 PM PDT 24
Finished May 21 12:55:52 PM PDT 24
Peak memory 229384 kb
Host smart-e4dbd3b1-c639-4bed-bf01-92e46a96f424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377876550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.377876550 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/21.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/21.kmac_error.251101042
Short name T536
Test name
Test status
Simulation time 7922394726 ps
CPU time 98.58 seconds
Started May 21 12:54:41 PM PDT 24
Finished May 21 12:56:20 PM PDT 24
Peak memory 243224 kb
Host smart-58fa5b56-1d09-4485-969d-05bd4cb44480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251101042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.251101042 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_error/latest

Test location /workspace/coverage/default/21.kmac_key_error.1473272344
Short name T5
Test name
Test status
Simulation time 1611653260 ps
CPU time 11.96 seconds
Started May 21 12:54:44 PM PDT 24
Finished May 21 12:54:57 PM PDT 24
Peak memory 218492 kb
Host smart-089fa28c-9d22-48b5-9591-dea6c814459a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473272344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.1473272344 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_key_error/latest

Test location /workspace/coverage/default/21.kmac_lc_escalation.3271595407
Short name T300
Test name
Test status
Simulation time 85151360 ps
CPU time 1.44 seconds
Started May 21 12:54:42 PM PDT 24
Finished May 21 12:54:44 PM PDT 24
Peak memory 219556 kb
Host smart-d7f6d159-5e36-4d6d-9947-86f385df6227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271595407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.3271595407 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/21.kmac_lc_escalation/latest

Test location /workspace/coverage/default/21.kmac_long_msg_and_output.3367964171
Short name T186
Test name
Test status
Simulation time 39883445103 ps
CPU time 1092.9 seconds
Started May 21 12:54:30 PM PDT 24
Finished May 21 01:12:45 PM PDT 24
Peak memory 298088 kb
Host smart-28a1560a-993e-4790-96c9-7eea9ba82b12
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367964171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_a
nd_output.3367964171 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/21.kmac_sideload.1748901502
Short name T982
Test name
Test status
Simulation time 13371386724 ps
CPU time 143.68 seconds
Started May 21 12:54:31 PM PDT 24
Finished May 21 12:56:56 PM PDT 24
Peak memory 235108 kb
Host smart-90c6c7e3-fc80-401f-9df3-4f76bb4d4a89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748901502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.1748901502 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_sideload/latest

Test location /workspace/coverage/default/21.kmac_smoke.2204752640
Short name T64
Test name
Test status
Simulation time 775486370 ps
CPU time 13.27 seconds
Started May 21 12:54:34 PM PDT 24
Finished May 21 12:54:48 PM PDT 24
Peak memory 223280 kb
Host smart-4c220657-6467-4374-ac69-11e2d80c6ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204752640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.2204752640 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_smoke/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac.3914486845
Short name T661
Test name
Test status
Simulation time 154504089 ps
CPU time 5.16 seconds
Started May 21 12:54:41 PM PDT 24
Finished May 21 12:54:47 PM PDT 24
Peak memory 226760 kb
Host smart-64a333dd-66e0-4b8a-b27e-a04ad64ae751
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914486845 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.kmac_test_vectors_kmac.3914486845 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac_xof.3737522072
Short name T1012
Test name
Test status
Simulation time 557024354 ps
CPU time 6.8 seconds
Started May 21 12:54:35 PM PDT 24
Finished May 21 12:54:43 PM PDT 24
Peak memory 218608 kb
Host smart-1c17760b-508b-4c3d-9171-d4532386b5b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737522072 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.kmac_test_vectors_kmac_xof.3737522072 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_224.3583115316
Short name T550
Test name
Test status
Simulation time 67362926921 ps
CPU time 2086.27 seconds
Started May 21 12:54:28 PM PDT 24
Finished May 21 01:29:16 PM PDT 24
Peak memory 395472 kb
Host smart-bbe52d87-72fa-4ab1-a69a-f5782d925286
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3583115316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_224.3583115316 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_256.2295227707
Short name T491
Test name
Test status
Simulation time 23367815867 ps
CPU time 1980.24 seconds
Started May 21 12:54:36 PM PDT 24
Finished May 21 01:27:37 PM PDT 24
Peak memory 387180 kb
Host smart-e3d5f3ca-d870-41c8-b512-1c896ed5ce7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2295227707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_256.2295227707 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_384.1282655302
Short name T876
Test name
Test status
Simulation time 58311558751 ps
CPU time 1452.8 seconds
Started May 21 12:54:41 PM PDT 24
Finished May 21 01:18:55 PM PDT 24
Peak memory 332572 kb
Host smart-80b03245-c95d-43e8-998b-84f33a08c347
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1282655302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_384.1282655302 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_512.452875428
Short name T665
Test name
Test status
Simulation time 34078508970 ps
CPU time 1258.47 seconds
Started May 21 12:54:40 PM PDT 24
Finished May 21 01:15:40 PM PDT 24
Peak memory 300836 kb
Host smart-32b501ad-8933-44f8-b5eb-2fc1a57fb7e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=452875428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_512.452875428 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_shake_128.3232259009
Short name T1039
Test name
Test status
Simulation time 362294473385 ps
CPU time 5496.46 seconds
Started May 21 12:54:39 PM PDT 24
Finished May 21 02:26:17 PM PDT 24
Peak memory 655528 kb
Host smart-b9a7bcc1-89fb-47b7-8bca-1850a1ce01e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3232259009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_128.3232259009 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_shake_256.2734211531
Short name T774
Test name
Test status
Simulation time 53214165918 ps
CPU time 4074.99 seconds
Started May 21 12:54:36 PM PDT 24
Finished May 21 02:02:32 PM PDT 24
Peak memory 554132 kb
Host smart-c2d0ff82-5c0b-4346-8ec1-0b7e9e3e512a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2734211531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_256.2734211531 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/22.kmac_alert_test.962462370
Short name T889
Test name
Test status
Simulation time 23102801 ps
CPU time 0.8 seconds
Started May 21 12:54:47 PM PDT 24
Finished May 21 12:54:50 PM PDT 24
Peak memory 218508 kb
Host smart-fe362576-e850-4307-ab7b-aa07e4c3c673
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962462370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.962462370 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/22.kmac_alert_test/latest

Test location /workspace/coverage/default/22.kmac_app.2037515259
Short name T461
Test name
Test status
Simulation time 2173626905 ps
CPU time 54.04 seconds
Started May 21 12:54:45 PM PDT 24
Finished May 21 12:55:40 PM PDT 24
Peak memory 235528 kb
Host smart-dcaafc2a-6d8a-47fd-9f3b-9415a8246a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037515259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.2037515259 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_app/latest

Test location /workspace/coverage/default/22.kmac_burst_write.273654400
Short name T551
Test name
Test status
Simulation time 24811397836 ps
CPU time 1115.63 seconds
Started May 21 12:54:40 PM PDT 24
Finished May 21 01:13:16 PM PDT 24
Peak memory 238376 kb
Host smart-99ce70e5-86fc-40d3-a3db-b30a2bef45d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273654400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.273654400 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_burst_write/latest

Test location /workspace/coverage/default/22.kmac_entropy_refresh.2623457316
Short name T1011
Test name
Test status
Simulation time 1569498618 ps
CPU time 42.62 seconds
Started May 21 12:54:47 PM PDT 24
Finished May 21 12:55:32 PM PDT 24
Peak memory 235072 kb
Host smart-f7f30135-a77f-4643-9bc6-7ae773713844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623457316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.2623457316 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/22.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/22.kmac_error.2114311700
Short name T147
Test name
Test status
Simulation time 48096008889 ps
CPU time 272.83 seconds
Started May 21 12:54:47 PM PDT 24
Finished May 21 12:59:22 PM PDT 24
Peak memory 258008 kb
Host smart-3e9c22a1-e7d8-4fde-8ae3-1abde3eaa7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114311700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.2114311700 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_error/latest

Test location /workspace/coverage/default/22.kmac_key_error.823455343
Short name T589
Test name
Test status
Simulation time 1388344571 ps
CPU time 9.84 seconds
Started May 21 12:54:49 PM PDT 24
Finished May 21 12:55:00 PM PDT 24
Peak memory 218516 kb
Host smart-00e67e8c-668b-479b-b787-c904e8354e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823455343 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.823455343 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_key_error/latest

Test location /workspace/coverage/default/22.kmac_lc_escalation.1219704298
Short name T685
Test name
Test status
Simulation time 63818169 ps
CPU time 1.28 seconds
Started May 21 12:54:52 PM PDT 24
Finished May 21 12:54:54 PM PDT 24
Peak memory 218704 kb
Host smart-1389b7f4-2d0c-48a4-a269-2770a7da6e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219704298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.1219704298 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/22.kmac_lc_escalation/latest

Test location /workspace/coverage/default/22.kmac_long_msg_and_output.1244399978
Short name T519
Test name
Test status
Simulation time 105389134706 ps
CPU time 730.84 seconds
Started May 21 12:54:44 PM PDT 24
Finished May 21 01:06:56 PM PDT 24
Peak memory 274128 kb
Host smart-8269ccf7-dd8e-4e5a-9284-f721a4251f00
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244399978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_a
nd_output.1244399978 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/22.kmac_sideload.2678121072
Short name T523
Test name
Test status
Simulation time 19045994983 ps
CPU time 358.02 seconds
Started May 21 12:54:46 PM PDT 24
Finished May 21 01:00:45 PM PDT 24
Peak memory 250012 kb
Host smart-3eaaa474-6b35-4ff8-8d5e-3d5dcbbc5dcf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678121072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.2678121072 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_sideload/latest

Test location /workspace/coverage/default/22.kmac_smoke.2330073746
Short name T351
Test name
Test status
Simulation time 7374497485 ps
CPU time 76.91 seconds
Started May 21 12:54:41 PM PDT 24
Finished May 21 12:55:59 PM PDT 24
Peak memory 226664 kb
Host smart-fc65f402-d5ed-4d0e-8536-e9d5ec61f139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330073746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.2330073746 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_smoke/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac.2130760777
Short name T190
Test name
Test status
Simulation time 224555141 ps
CPU time 5.69 seconds
Started May 21 12:54:44 PM PDT 24
Finished May 21 12:54:51 PM PDT 24
Peak memory 218664 kb
Host smart-1bd9b4c7-e746-4fd1-99c0-f4f3447d575b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130760777 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.kmac_test_vectors_kmac.2130760777 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac_xof.3332817528
Short name T915
Test name
Test status
Simulation time 242595479 ps
CPU time 6.1 seconds
Started May 21 12:54:41 PM PDT 24
Finished May 21 12:54:49 PM PDT 24
Peak memory 218528 kb
Host smart-7d4088af-b4eb-4b0c-b929-75607d2b63ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332817528 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.kmac_test_vectors_kmac_xof.3332817528 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_224.398179451
Short name T928
Test name
Test status
Simulation time 20325557410 ps
CPU time 1950.33 seconds
Started May 21 12:54:44 PM PDT 24
Finished May 21 01:27:15 PM PDT 24
Peak memory 394160 kb
Host smart-3d1fe043-56f2-4d45-a4ee-06ac09d422f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=398179451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_224.398179451 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_256.1974408424
Short name T866
Test name
Test status
Simulation time 376964659199 ps
CPU time 2361.66 seconds
Started May 21 12:54:43 PM PDT 24
Finished May 21 01:34:06 PM PDT 24
Peak memory 389520 kb
Host smart-f5b2f08d-2900-4a0c-a7f7-df4f21f0603d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1974408424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_256.1974408424 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_384.2877829697
Short name T777
Test name
Test status
Simulation time 16068853980 ps
CPU time 1481.12 seconds
Started May 21 12:54:44 PM PDT 24
Finished May 21 01:19:26 PM PDT 24
Peak memory 342560 kb
Host smart-c4fada7f-e898-494b-8d26-bf76d14fddfc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2877829697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_384.2877829697 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_512.4128768600
Short name T802
Test name
Test status
Simulation time 34501807143 ps
CPU time 1266.61 seconds
Started May 21 12:54:43 PM PDT 24
Finished May 21 01:15:51 PM PDT 24
Peak memory 300872 kb
Host smart-a278b178-5d66-443d-b767-5c0efaefcde7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4128768600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_512.4128768600 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_shake_128.2563283446
Short name T591
Test name
Test status
Simulation time 367464753115 ps
CPU time 5633.07 seconds
Started May 21 12:54:42 PM PDT 24
Finished May 21 02:28:37 PM PDT 24
Peak memory 651684 kb
Host smart-28992255-932f-4e72-8424-b51ac34a55b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2563283446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_128.2563283446 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_shake_256.523018756
Short name T547
Test name
Test status
Simulation time 752671842886 ps
CPU time 4679.09 seconds
Started May 21 12:54:44 PM PDT 24
Finished May 21 02:12:45 PM PDT 24
Peak memory 571248 kb
Host smart-724c3b6f-8eed-466c-84f1-a6093b62ee4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=523018756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_256.523018756 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/23.kmac_alert_test.4059983273
Short name T894
Test name
Test status
Simulation time 24468734 ps
CPU time 0.86 seconds
Started May 21 12:54:58 PM PDT 24
Finished May 21 12:55:00 PM PDT 24
Peak memory 218472 kb
Host smart-f24d0d36-e54c-41f2-9db4-bf43cccb3995
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059983273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.4059983273 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_alert_test/latest

Test location /workspace/coverage/default/23.kmac_app.1571613256
Short name T891
Test name
Test status
Simulation time 5011978505 ps
CPU time 357.73 seconds
Started May 21 12:54:46 PM PDT 24
Finished May 21 01:00:45 PM PDT 24
Peak memory 250364 kb
Host smart-34c91595-054d-4aaf-a72d-f987ee101617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571613256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.1571613256 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_app/latest

Test location /workspace/coverage/default/23.kmac_burst_write.2588019298
Short name T948
Test name
Test status
Simulation time 23872714777 ps
CPU time 1241.43 seconds
Started May 21 12:54:47 PM PDT 24
Finished May 21 01:15:31 PM PDT 24
Peak memory 238096 kb
Host smart-aff64113-be78-4d7e-8d24-579270bed5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588019298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.2588019298 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_burst_write/latest

Test location /workspace/coverage/default/23.kmac_entropy_refresh.383551024
Short name T452
Test name
Test status
Simulation time 5413339668 ps
CPU time 103.25 seconds
Started May 21 12:54:47 PM PDT 24
Finished May 21 12:56:32 PM PDT 24
Peak memory 233592 kb
Host smart-ba5c1289-7591-46d9-a63b-4fc3a3fe57e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383551024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.383551024 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/23.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/23.kmac_error.2933009071
Short name T999
Test name
Test status
Simulation time 68476562186 ps
CPU time 392.41 seconds
Started May 21 12:54:48 PM PDT 24
Finished May 21 01:01:22 PM PDT 24
Peak memory 259460 kb
Host smart-684fafb3-c00d-45e2-a3be-61f7cb347874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933009071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.2933009071 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_error/latest

Test location /workspace/coverage/default/23.kmac_key_error.4043439769
Short name T216
Test name
Test status
Simulation time 1869311650 ps
CPU time 9.63 seconds
Started May 21 12:54:50 PM PDT 24
Finished May 21 12:55:01 PM PDT 24
Peak memory 218532 kb
Host smart-e9afcd69-3fa8-40da-b799-ce09fe4974a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043439769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.4043439769 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_key_error/latest

Test location /workspace/coverage/default/23.kmac_lc_escalation.3736076862
Short name T959
Test name
Test status
Simulation time 66949790 ps
CPU time 1.35 seconds
Started May 21 12:54:55 PM PDT 24
Finished May 21 12:54:58 PM PDT 24
Peak memory 218644 kb
Host smart-03e44ac0-fb6a-452f-9274-6fab9473e30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736076862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.3736076862 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/23.kmac_lc_escalation/latest

Test location /workspace/coverage/default/23.kmac_long_msg_and_output.1156956787
Short name T699
Test name
Test status
Simulation time 172527837431 ps
CPU time 3012.65 seconds
Started May 21 12:54:47 PM PDT 24
Finished May 21 01:45:02 PM PDT 24
Peak memory 469496 kb
Host smart-81f2b5b1-d4fa-4743-a3d0-26f638d351e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156956787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_a
nd_output.1156956787 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/23.kmac_sideload.413062134
Short name T403
Test name
Test status
Simulation time 3310909285 ps
CPU time 267.94 seconds
Started May 21 12:54:48 PM PDT 24
Finished May 21 12:59:18 PM PDT 24
Peak memory 246480 kb
Host smart-8ae6dcd2-7c6d-47d0-9f2a-f2c568d9941a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413062134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.413062134 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_sideload/latest

Test location /workspace/coverage/default/23.kmac_smoke.1268753787
Short name T766
Test name
Test status
Simulation time 6884854080 ps
CPU time 42.81 seconds
Started May 21 12:54:53 PM PDT 24
Finished May 21 12:55:38 PM PDT 24
Peak memory 226772 kb
Host smart-62ddf922-5ed4-4b83-8dab-fd69bb6fc811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268753787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.1268753787 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_smoke/latest

Test location /workspace/coverage/default/23.kmac_stress_all.2679945900
Short name T1008
Test name
Test status
Simulation time 31050726527 ps
CPU time 834.2 seconds
Started May 21 12:54:55 PM PDT 24
Finished May 21 01:08:51 PM PDT 24
Peak memory 312516 kb
Host smart-b075039d-3935-4a97-99ed-9c64383c462e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2679945900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.2679945900 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_stress_all/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac.1677286326
Short name T469
Test name
Test status
Simulation time 1928480643 ps
CPU time 7.39 seconds
Started May 21 12:54:52 PM PDT 24
Finished May 21 12:55:00 PM PDT 24
Peak memory 218644 kb
Host smart-502b39a4-5a8a-4871-bd18-efbe30c39cc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677286326 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.kmac_test_vectors_kmac.1677286326 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac_xof.59749229
Short name T202
Test name
Test status
Simulation time 247496781 ps
CPU time 6.35 seconds
Started May 21 12:54:47 PM PDT 24
Finished May 21 12:54:56 PM PDT 24
Peak memory 226696 kb
Host smart-68cc3b9d-382a-40ec-8ec6-d9dae95159ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59749229 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.kmac_test_vectors_kmac_xof.59749229 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_224.834303186
Short name T513
Test name
Test status
Simulation time 40552025926 ps
CPU time 1727.68 seconds
Started May 21 12:54:48 PM PDT 24
Finished May 21 01:23:37 PM PDT 24
Peak memory 391756 kb
Host smart-63c3fbf1-3f99-4d1a-afc0-0b453dd65639
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=834303186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_224.834303186 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_256.1647933039
Short name T474
Test name
Test status
Simulation time 82112062726 ps
CPU time 2016.83 seconds
Started May 21 12:54:51 PM PDT 24
Finished May 21 01:28:29 PM PDT 24
Peak memory 397076 kb
Host smart-5fda96ba-8205-4227-8d18-be6d8f7849e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1647933039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_256.1647933039 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_384.4247630694
Short name T843
Test name
Test status
Simulation time 15109229468 ps
CPU time 1551.61 seconds
Started May 21 12:54:51 PM PDT 24
Finished May 21 01:20:43 PM PDT 24
Peak memory 337092 kb
Host smart-3296856e-beed-4a93-b83c-352a2c34b7e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4247630694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_384.4247630694 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_512.3623592212
Short name T295
Test name
Test status
Simulation time 10642426612 ps
CPU time 1093.38 seconds
Started May 21 12:54:47 PM PDT 24
Finished May 21 01:13:03 PM PDT 24
Peak memory 296648 kb
Host smart-207b79c9-8ac6-413c-968a-889bd1d5bf34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3623592212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_512.3623592212 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_128.425024118
Short name T236
Test name
Test status
Simulation time 1048717554932 ps
CPU time 5898.55 seconds
Started May 21 12:54:49 PM PDT 24
Finished May 21 02:33:09 PM PDT 24
Peak memory 667624 kb
Host smart-6deeb961-2630-4749-9a5d-eefbb47684be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=425024118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_128.425024118 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_256.1732680682
Short name T746
Test name
Test status
Simulation time 200431271423 ps
CPU time 4848.38 seconds
Started May 21 12:54:47 PM PDT 24
Finished May 21 02:15:38 PM PDT 24
Peak memory 579656 kb
Host smart-76def175-1924-4883-9621-2cd2b1f6060c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1732680682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_256.1732680682 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/24.kmac_alert_test.73118205
Short name T377
Test name
Test status
Simulation time 89294492 ps
CPU time 0.8 seconds
Started May 21 12:54:59 PM PDT 24
Finished May 21 12:55:02 PM PDT 24
Peak memory 218392 kb
Host smart-df705598-71e5-4f2b-9d29-0e80395b1fa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73118205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.73118205 +enable_mas
king=1 +sw_key_masked=0
Directory /workspace/24.kmac_alert_test/latest

Test location /workspace/coverage/default/24.kmac_app.2308572681
Short name T404
Test name
Test status
Simulation time 14823988311 ps
CPU time 90.08 seconds
Started May 21 12:54:54 PM PDT 24
Finished May 21 12:56:26 PM PDT 24
Peak memory 232564 kb
Host smart-25932ef7-1b76-4f3c-a0fe-92c55bd97df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308572681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.2308572681 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_app/latest

Test location /workspace/coverage/default/24.kmac_burst_write.888732510
Short name T34
Test name
Test status
Simulation time 55561764546 ps
CPU time 333.38 seconds
Started May 21 12:54:52 PM PDT 24
Finished May 21 01:00:27 PM PDT 24
Peak memory 230864 kb
Host smart-e0c137fc-006b-4d96-8403-2d73ad2a61af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888732510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.888732510 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_burst_write/latest

Test location /workspace/coverage/default/24.kmac_entropy_refresh.872821935
Short name T139
Test name
Test status
Simulation time 2742311605 ps
CPU time 21.67 seconds
Started May 21 12:54:58 PM PDT 24
Finished May 21 12:55:21 PM PDT 24
Peak memory 226708 kb
Host smart-8790dc7e-3d0f-4cc7-9341-2f5440f45139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872821935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.872821935 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/24.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/24.kmac_error.2619174265
Short name T975
Test name
Test status
Simulation time 2003477146 ps
CPU time 147.83 seconds
Started May 21 12:54:54 PM PDT 24
Finished May 21 12:57:24 PM PDT 24
Peak memory 243052 kb
Host smart-f551581f-4a34-47c4-87d8-248280e80525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619174265 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.2619174265 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_error/latest

Test location /workspace/coverage/default/24.kmac_key_error.3067957410
Short name T201
Test name
Test status
Simulation time 2577259827 ps
CPU time 10.13 seconds
Started May 21 12:54:58 PM PDT 24
Finished May 21 12:55:10 PM PDT 24
Peak memory 218512 kb
Host smart-c98110ce-de15-4a6f-8909-589be8b2e730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067957410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.3067957410 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_key_error/latest

Test location /workspace/coverage/default/24.kmac_lc_escalation.4275374425
Short name T51
Test name
Test status
Simulation time 83541203 ps
CPU time 1.47 seconds
Started May 21 12:54:53 PM PDT 24
Finished May 21 12:54:56 PM PDT 24
Peak memory 226704 kb
Host smart-cbc56dfa-f56b-4729-bddc-4ba55d38b936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275374425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.4275374425 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/24.kmac_lc_escalation/latest

Test location /workspace/coverage/default/24.kmac_long_msg_and_output.1200334240
Short name T542
Test name
Test status
Simulation time 24774242288 ps
CPU time 2468.73 seconds
Started May 21 12:54:52 PM PDT 24
Finished May 21 01:36:03 PM PDT 24
Peak memory 447200 kb
Host smart-98d75d52-70cf-4b5f-b393-632ffff16c36
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200334240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_a
nd_output.1200334240 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/24.kmac_sideload.3688237672
Short name T496
Test name
Test status
Simulation time 9775856062 ps
CPU time 462.04 seconds
Started May 21 12:54:55 PM PDT 24
Finished May 21 01:02:39 PM PDT 24
Peak memory 255324 kb
Host smart-11b2bc7b-d755-4f8b-91b8-64c210b1062a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688237672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.3688237672 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_sideload/latest

Test location /workspace/coverage/default/24.kmac_smoke.270679097
Short name T630
Test name
Test status
Simulation time 227126538 ps
CPU time 6.76 seconds
Started May 21 12:54:55 PM PDT 24
Finished May 21 12:55:03 PM PDT 24
Peak memory 226684 kb
Host smart-a88f5dad-d2ce-43f4-aada-af74b0e29bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270679097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.270679097 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_smoke/latest

Test location /workspace/coverage/default/24.kmac_stress_all.3769544919
Short name T723
Test name
Test status
Simulation time 250757431229 ps
CPU time 3367.57 seconds
Started May 21 12:54:53 PM PDT 24
Finished May 21 01:51:04 PM PDT 24
Peak memory 492612 kb
Host smart-6ad22938-751a-49c0-b1d5-c79c4d1bf2d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3769544919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.3769544919 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_stress_all/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac.4197841460
Short name T793
Test name
Test status
Simulation time 1244599022 ps
CPU time 5.49 seconds
Started May 21 12:54:55 PM PDT 24
Finished May 21 12:55:03 PM PDT 24
Peak memory 218664 kb
Host smart-3566e587-0da6-40b3-97c4-4636e671c88c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197841460 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.kmac_test_vectors_kmac.4197841460 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac_xof.1609230139
Short name T352
Test name
Test status
Simulation time 105275043 ps
CPU time 5.23 seconds
Started May 21 12:54:53 PM PDT 24
Finished May 21 12:55:00 PM PDT 24
Peak memory 218604 kb
Host smart-d7484a70-d495-49b9-a1ef-8a85dd821150
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609230139 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.kmac_test_vectors_kmac_xof.1609230139 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_224.1680005941
Short name T35
Test name
Test status
Simulation time 133517842233 ps
CPU time 2294.11 seconds
Started May 21 12:54:58 PM PDT 24
Finished May 21 01:33:12 PM PDT 24
Peak memory 397428 kb
Host smart-4af98398-7a3b-4a37-9093-7aa493a6a6ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1680005941 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_224.1680005941 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_384.311470408
Short name T687
Test name
Test status
Simulation time 142420953568 ps
CPU time 1822.92 seconds
Started May 21 12:54:54 PM PDT 24
Finished May 21 01:25:20 PM PDT 24
Peak memory 337948 kb
Host smart-811c5597-8cb6-4203-a266-81b6889f9c22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=311470408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_384.311470408 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_512.3340351589
Short name T441
Test name
Test status
Simulation time 34346303779 ps
CPU time 1267.05 seconds
Started May 21 12:54:54 PM PDT 24
Finished May 21 01:16:03 PM PDT 24
Peak memory 301820 kb
Host smart-5b354776-9b9a-4c8a-9df3-fb0442eb2037
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3340351589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_512.3340351589 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_128.3877071199
Short name T599
Test name
Test status
Simulation time 211666450044 ps
CPU time 4982.33 seconds
Started May 21 12:54:53 PM PDT 24
Finished May 21 02:17:59 PM PDT 24
Peak memory 639536 kb
Host smart-1becb115-f627-4c7d-9a49-532c507894ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3877071199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_128.3877071199 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_256.4226885768
Short name T602
Test name
Test status
Simulation time 211664953901 ps
CPU time 4546.33 seconds
Started May 21 12:54:54 PM PDT 24
Finished May 21 02:10:43 PM PDT 24
Peak memory 574108 kb
Host smart-bb5d5e89-a26f-4218-b5e0-4d162ae3843c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4226885768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_256.4226885768 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/25.kmac_alert_test.3140974739
Short name T254
Test name
Test status
Simulation time 24876549 ps
CPU time 0.93 seconds
Started May 21 12:54:59 PM PDT 24
Finished May 21 12:55:02 PM PDT 24
Peak memory 218828 kb
Host smart-c34b0bdd-8153-49cc-93d0-70a5da955c94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140974739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.3140974739 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_alert_test/latest

Test location /workspace/coverage/default/25.kmac_app.1883017812
Short name T462
Test name
Test status
Simulation time 24612905921 ps
CPU time 251.77 seconds
Started May 21 12:54:59 PM PDT 24
Finished May 21 12:59:12 PM PDT 24
Peak memory 246796 kb
Host smart-dc9d20a9-de63-421b-be6d-74f2c62a42be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883017812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.1883017812 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_app/latest

Test location /workspace/coverage/default/25.kmac_burst_write.1381365630
Short name T986
Test name
Test status
Simulation time 20618279191 ps
CPU time 933.42 seconds
Started May 21 12:54:59 PM PDT 24
Finished May 21 01:10:34 PM PDT 24
Peak memory 236988 kb
Host smart-2d02867a-6a15-4240-896e-173662fac91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381365630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.1381365630 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_burst_write/latest

Test location /workspace/coverage/default/25.kmac_entropy_refresh.4238692360
Short name T637
Test name
Test status
Simulation time 15098429398 ps
CPU time 318.2 seconds
Started May 21 12:55:05 PM PDT 24
Finished May 21 01:00:25 PM PDT 24
Peak memory 249552 kb
Host smart-d0b65ebc-c6d0-430b-a858-d3e942c1a253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238692360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.4238692360 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/25.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/25.kmac_error.3524907809
Short name T932
Test name
Test status
Simulation time 7413189484 ps
CPU time 170.64 seconds
Started May 21 12:55:02 PM PDT 24
Finished May 21 12:57:53 PM PDT 24
Peak memory 251352 kb
Host smart-8bb90abf-401c-4469-b99a-95c1027fd69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524907809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.3524907809 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_error/latest

Test location /workspace/coverage/default/25.kmac_key_error.2794817543
Short name T985
Test name
Test status
Simulation time 69064745 ps
CPU time 1.35 seconds
Started May 21 12:55:05 PM PDT 24
Finished May 21 12:55:08 PM PDT 24
Peak memory 218452 kb
Host smart-bb2514c1-ab40-4a29-9824-abead48d0ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794817543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.2794817543 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_key_error/latest

Test location /workspace/coverage/default/25.kmac_long_msg_and_output.193598315
Short name T1016
Test name
Test status
Simulation time 10694351625 ps
CPU time 80.07 seconds
Started May 21 12:55:02 PM PDT 24
Finished May 21 12:56:23 PM PDT 24
Peak memory 239552 kb
Host smart-b5a85b21-c590-417a-b60d-2209a9ec434e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193598315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_an
d_output.193598315 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/25.kmac_sideload.111039452
Short name T942
Test name
Test status
Simulation time 31866428115 ps
CPU time 96.23 seconds
Started May 21 12:55:09 PM PDT 24
Finished May 21 12:56:46 PM PDT 24
Peak memory 241168 kb
Host smart-929262b7-9cf7-417a-a35b-b7c1ca62e8e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111039452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.111039452 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_sideload/latest

Test location /workspace/coverage/default/25.kmac_smoke.712832104
Short name T330
Test name
Test status
Simulation time 28864158969 ps
CPU time 77.33 seconds
Started May 21 12:55:01 PM PDT 24
Finished May 21 12:56:20 PM PDT 24
Peak memory 226724 kb
Host smart-6d171bf4-7be7-4d17-a22d-528a2bca809c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712832104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.712832104 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_smoke/latest

Test location /workspace/coverage/default/25.kmac_stress_all.296422961
Short name T262
Test name
Test status
Simulation time 26783984684 ps
CPU time 647.69 seconds
Started May 21 12:55:05 PM PDT 24
Finished May 21 01:05:55 PM PDT 24
Peak memory 281744 kb
Host smart-3e670c46-8dd5-44a3-9282-16e92b1bda06
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=296422961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.296422961 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_stress_all/latest

Test location /workspace/coverage/default/25.kmac_stress_all_with_rand_reset.3561575662
Short name T856
Test name
Test status
Simulation time 166567928740 ps
CPU time 2585.15 seconds
Started May 21 12:55:06 PM PDT 24
Finished May 21 01:38:13 PM PDT 24
Peak memory 381780 kb
Host smart-d7f93375-8e9e-4324-9175-3c7af0ae9484
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3561575662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all_with_rand_reset.3561575662 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac.3668672807
Short name T442
Test name
Test status
Simulation time 830786929 ps
CPU time 5.95 seconds
Started May 21 12:55:02 PM PDT 24
Finished May 21 12:55:09 PM PDT 24
Peak memory 226692 kb
Host smart-e41350c0-e81f-4515-bdf6-fe60ac28faa1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668672807 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.kmac_test_vectors_kmac.3668672807 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac_xof.3979011427
Short name T174
Test name
Test status
Simulation time 489482334 ps
CPU time 5.99 seconds
Started May 21 12:55:01 PM PDT 24
Finished May 21 12:55:08 PM PDT 24
Peak memory 218652 kb
Host smart-080e2b96-dabf-430c-8b3e-2ff50c24d344
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979011427 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.kmac_test_vectors_kmac_xof.3979011427 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_224.3088853662
Short name T276
Test name
Test status
Simulation time 63859048634 ps
CPU time 2019.43 seconds
Started May 21 12:55:05 PM PDT 24
Finished May 21 01:28:47 PM PDT 24
Peak memory 380896 kb
Host smart-04070131-6a76-426d-a446-2706be7b9885
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3088853662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_224.3088853662 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_256.130501325
Short name T951
Test name
Test status
Simulation time 28668368855 ps
CPU time 1917.41 seconds
Started May 21 12:55:01 PM PDT 24
Finished May 21 01:27:00 PM PDT 24
Peak memory 386152 kb
Host smart-6366db4f-225f-4bdf-b1f2-a27881113bc8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=130501325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_256.130501325 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_384.249587988
Short name T209
Test name
Test status
Simulation time 124085472550 ps
CPU time 1636.14 seconds
Started May 21 12:55:00 PM PDT 24
Finished May 21 01:22:18 PM PDT 24
Peak memory 344836 kb
Host smart-a61b6ec0-cc93-498f-ae1b-1cddadd82b6e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=249587988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_384.249587988 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_512.4152519407
Short name T750
Test name
Test status
Simulation time 67960979718 ps
CPU time 1246.55 seconds
Started May 21 12:55:00 PM PDT 24
Finished May 21 01:15:48 PM PDT 24
Peak memory 301500 kb
Host smart-dee67109-6e71-43be-be86-a25e580fc634
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4152519407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_512.4152519407 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_shake_128.912848745
Short name T778
Test name
Test status
Simulation time 849587369250 ps
CPU time 4981.86 seconds
Started May 21 12:55:06 PM PDT 24
Finished May 21 02:18:10 PM PDT 24
Peak memory 650904 kb
Host smart-9cf2f29a-7531-4807-8f65-3476aff40b9a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=912848745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_128.912848745 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_shake_256.2549795126
Short name T965
Test name
Test status
Simulation time 496414927784 ps
CPU time 5091.13 seconds
Started May 21 12:55:09 PM PDT 24
Finished May 21 02:20:02 PM PDT 24
Peak memory 569848 kb
Host smart-7a4de959-cfd5-4e1b-83b6-960888862d35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2549795126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_256.2549795126 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/26.kmac_alert_test.559312824
Short name T486
Test name
Test status
Simulation time 47841405 ps
CPU time 0.83 seconds
Started May 21 12:55:08 PM PDT 24
Finished May 21 12:55:10 PM PDT 24
Peak memory 218480 kb
Host smart-6352ebef-1ef1-43ef-893e-b4359a57dbf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559312824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.559312824 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/26.kmac_alert_test/latest

Test location /workspace/coverage/default/26.kmac_app.2378682860
Short name T652
Test name
Test status
Simulation time 23485941617 ps
CPU time 414.93 seconds
Started May 21 12:55:13 PM PDT 24
Finished May 21 01:02:10 PM PDT 24
Peak memory 255152 kb
Host smart-a8e7cb30-00fa-4fb1-b35b-0b3957d3199f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378682860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.2378682860 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_app/latest

Test location /workspace/coverage/default/26.kmac_burst_write.518244144
Short name T731
Test name
Test status
Simulation time 5850787350 ps
CPU time 247.67 seconds
Started May 21 12:55:07 PM PDT 24
Finished May 21 12:59:16 PM PDT 24
Peak memory 229012 kb
Host smart-2fade3c4-e8cb-43ac-b08e-bcfc70128331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518244144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.518244144 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_burst_write/latest

Test location /workspace/coverage/default/26.kmac_entropy_refresh.4166101287
Short name T1045
Test name
Test status
Simulation time 452221576 ps
CPU time 11.19 seconds
Started May 21 12:55:05 PM PDT 24
Finished May 21 12:55:18 PM PDT 24
Peak memory 226668 kb
Host smart-5d8a17ad-1b42-4536-9582-e3d34a1a6b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166101287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.4166101287 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/26.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/26.kmac_error.3995114030
Short name T1020
Test name
Test status
Simulation time 1327232894 ps
CPU time 97.92 seconds
Started May 21 12:55:06 PM PDT 24
Finished May 21 12:56:46 PM PDT 24
Peak memory 243096 kb
Host smart-5b554eb8-62ba-4060-9d06-53c874ae6110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995114030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.3995114030 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_error/latest

Test location /workspace/coverage/default/26.kmac_key_error.985182246
Short name T100
Test name
Test status
Simulation time 440302432 ps
CPU time 1.81 seconds
Started May 21 12:55:05 PM PDT 24
Finished May 21 12:55:09 PM PDT 24
Peak memory 218520 kb
Host smart-ef02341e-5646-4776-8eef-d102bf493257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985182246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.985182246 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_key_error/latest

Test location /workspace/coverage/default/26.kmac_long_msg_and_output.1680499764
Short name T1048
Test name
Test status
Simulation time 69485555239 ps
CPU time 1789.28 seconds
Started May 21 12:55:13 PM PDT 24
Finished May 21 01:25:05 PM PDT 24
Peak memory 356112 kb
Host smart-aece5e79-f73e-4fa3-8346-3e4d296362f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680499764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_a
nd_output.1680499764 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/26.kmac_sideload.289521894
Short name T880
Test name
Test status
Simulation time 55155924648 ps
CPU time 334.94 seconds
Started May 21 12:54:59 PM PDT 24
Finished May 21 01:00:36 PM PDT 24
Peak memory 243420 kb
Host smart-c51acd6b-9a56-4ca1-bd18-63d2ae0cbaf4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289521894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.289521894 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_sideload/latest

Test location /workspace/coverage/default/26.kmac_smoke.1214286011
Short name T799
Test name
Test status
Simulation time 2959229509 ps
CPU time 31.19 seconds
Started May 21 12:54:59 PM PDT 24
Finished May 21 12:55:32 PM PDT 24
Peak memory 218612 kb
Host smart-2a16ea10-b546-43c9-9faf-b103f3381ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214286011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.1214286011 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_smoke/latest

Test location /workspace/coverage/default/26.kmac_stress_all.3483676578
Short name T663
Test name
Test status
Simulation time 38891144967 ps
CPU time 303.62 seconds
Started May 21 12:55:04 PM PDT 24
Finished May 21 01:00:08 PM PDT 24
Peak memory 287280 kb
Host smart-54adcfb7-da57-4599-ac16-9853753df9d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3483676578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.3483676578 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_stress_all/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac.2491208663
Short name T1009
Test name
Test status
Simulation time 425765882 ps
CPU time 6.52 seconds
Started May 21 12:55:13 PM PDT 24
Finished May 21 12:55:22 PM PDT 24
Peak memory 219712 kb
Host smart-7ae5aa9f-6d6f-4de6-9782-2b15ae21ecc6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491208663 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.kmac_test_vectors_kmac.2491208663 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac_xof.1287627309
Short name T1053
Test name
Test status
Simulation time 224222921 ps
CPU time 6.52 seconds
Started May 21 12:55:05 PM PDT 24
Finished May 21 12:55:13 PM PDT 24
Peak memory 226596 kb
Host smart-148b930f-fc27-47f5-a08e-fd6cd4dd2c03
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287627309 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.kmac_test_vectors_kmac_xof.1287627309 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_224.3378402931
Short name T724
Test name
Test status
Simulation time 281302674664 ps
CPU time 2221.65 seconds
Started May 21 12:54:59 PM PDT 24
Finished May 21 01:32:02 PM PDT 24
Peak memory 403880 kb
Host smart-27abd06e-d846-48a9-b6e4-ee1b757ddb83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3378402931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_224.3378402931 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_256.2422883631
Short name T207
Test name
Test status
Simulation time 38592633294 ps
CPU time 1814.64 seconds
Started May 21 12:55:04 PM PDT 24
Finished May 21 01:25:19 PM PDT 24
Peak memory 389456 kb
Host smart-62eb4929-65c9-4e5e-8bf0-7fba281e7937
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2422883631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_256.2422883631 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_384.3838097462
Short name T563
Test name
Test status
Simulation time 47631094154 ps
CPU time 1717.26 seconds
Started May 21 12:55:00 PM PDT 24
Finished May 21 01:23:39 PM PDT 24
Peak memory 339000 kb
Host smart-9f4de050-fa66-4b9b-aadc-45876cad2f01
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3838097462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_384.3838097462 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_512.3301131185
Short name T184
Test name
Test status
Simulation time 21689090278 ps
CPU time 1117.39 seconds
Started May 21 12:55:04 PM PDT 24
Finished May 21 01:13:42 PM PDT 24
Peak memory 298220 kb
Host smart-d9696fd4-fc5e-4c27-be88-9b706bdcbd1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3301131185 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_512.3301131185 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_128.2795219194
Short name T332
Test name
Test status
Simulation time 59832095793 ps
CPU time 5210.62 seconds
Started May 21 12:55:13 PM PDT 24
Finished May 21 02:22:07 PM PDT 24
Peak memory 648844 kb
Host smart-f07a901e-caf5-4f57-b510-e855cae98ef6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2795219194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_128.2795219194 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_256.4127180184
Short name T849
Test name
Test status
Simulation time 140533262917 ps
CPU time 4723.07 seconds
Started May 21 12:55:10 PM PDT 24
Finished May 21 02:13:55 PM PDT 24
Peak memory 574404 kb
Host smart-d94d658b-c44f-4a5e-b441-074c0da1c81c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4127180184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_256.4127180184 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/27.kmac_alert_test.3424209340
Short name T96
Test name
Test status
Simulation time 14131226 ps
CPU time 0.82 seconds
Started May 21 12:55:10 PM PDT 24
Finished May 21 12:55:12 PM PDT 24
Peak memory 218464 kb
Host smart-b1dd2e78-7ba5-4c5d-9b0b-e8cece6f304b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424209340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.3424209340 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_alert_test/latest

Test location /workspace/coverage/default/27.kmac_app.69166306
Short name T780
Test name
Test status
Simulation time 26455403408 ps
CPU time 207.16 seconds
Started May 21 12:55:12 PM PDT 24
Finished May 21 12:58:41 PM PDT 24
Peak memory 241768 kb
Host smart-8ab644a3-2a4a-40d6-b82a-2f0a464b226e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69166306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.69166306 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_app/latest

Test location /workspace/coverage/default/27.kmac_burst_write.645491463
Short name T457
Test name
Test status
Simulation time 5074175554 ps
CPU time 576.83 seconds
Started May 21 12:55:13 PM PDT 24
Finished May 21 01:04:52 PM PDT 24
Peak memory 232868 kb
Host smart-141712e9-b060-44b9-a65a-9e3545de9759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645491463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.645491463 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_burst_write/latest

Test location /workspace/coverage/default/27.kmac_entropy_refresh.3570953966
Short name T879
Test name
Test status
Simulation time 2222961841 ps
CPU time 45.17 seconds
Started May 21 12:55:11 PM PDT 24
Finished May 21 12:55:58 PM PDT 24
Peak memory 227376 kb
Host smart-f6786c36-1d6c-41de-8f94-282363f6adb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570953966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.3570953966 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/27.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/27.kmac_error.1523890738
Short name T840
Test name
Test status
Simulation time 2471821043 ps
CPU time 209.74 seconds
Started May 21 12:55:13 PM PDT 24
Finished May 21 12:58:45 PM PDT 24
Peak memory 259044 kb
Host smart-dae44842-a986-47be-a8d0-5667a41cdfe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523890738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.1523890738 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_error/latest

Test location /workspace/coverage/default/27.kmac_key_error.4192079263
Short name T701
Test name
Test status
Simulation time 319486003 ps
CPU time 3.64 seconds
Started May 21 12:55:12 PM PDT 24
Finished May 21 12:55:17 PM PDT 24
Peak memory 218536 kb
Host smart-0e64b9e5-dc0d-4942-8a8e-7fb73321ec09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192079263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.4192079263 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_key_error/latest

Test location /workspace/coverage/default/27.kmac_lc_escalation.1993056401
Short name T729
Test name
Test status
Simulation time 42310081 ps
CPU time 1.28 seconds
Started May 21 12:55:10 PM PDT 24
Finished May 21 12:55:13 PM PDT 24
Peak memory 218564 kb
Host smart-a990a75b-7d0a-4584-bd0e-0e05d1cdd33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993056401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.1993056401 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/27.kmac_lc_escalation/latest

Test location /workspace/coverage/default/27.kmac_long_msg_and_output.344962874
Short name T956
Test name
Test status
Simulation time 9547986548 ps
CPU time 1014.2 seconds
Started May 21 12:55:04 PM PDT 24
Finished May 21 01:11:59 PM PDT 24
Peak memory 310548 kb
Host smart-99bf87bc-c87a-49fd-bfb3-2506e830787b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344962874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_an
d_output.344962874 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/27.kmac_sideload.3081579845
Short name T483
Test name
Test status
Simulation time 44644772749 ps
CPU time 525.64 seconds
Started May 21 12:55:09 PM PDT 24
Finished May 21 01:03:56 PM PDT 24
Peak memory 256952 kb
Host smart-694d153e-4fa4-49be-9785-8685f0f627bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081579845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.3081579845 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_sideload/latest

Test location /workspace/coverage/default/27.kmac_smoke.1267281103
Short name T260
Test name
Test status
Simulation time 23028207749 ps
CPU time 98.35 seconds
Started May 21 12:55:09 PM PDT 24
Finished May 21 12:56:49 PM PDT 24
Peak memory 226696 kb
Host smart-476fc5d2-28a8-4d03-a7e7-e92531ae7b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267281103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.1267281103 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_smoke/latest

Test location /workspace/coverage/default/27.kmac_stress_all.62353677
Short name T8
Test name
Test status
Simulation time 30994211518 ps
CPU time 781.65 seconds
Started May 21 12:55:11 PM PDT 24
Finished May 21 01:08:15 PM PDT 24
Peak memory 325108 kb
Host smart-722cc35f-13ff-4376-b885-e31c89c70d13
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=62353677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.62353677 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_stress_all/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac.3335405314
Short name T364
Test name
Test status
Simulation time 1198061857 ps
CPU time 6.23 seconds
Started May 21 12:55:11 PM PDT 24
Finished May 21 12:55:19 PM PDT 24
Peak memory 226644 kb
Host smart-5dbc7791-ad56-44ed-b48f-6f4bac0b0c7a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335405314 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.kmac_test_vectors_kmac.3335405314 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac_xof.3146449632
Short name T367
Test name
Test status
Simulation time 252117227 ps
CPU time 6.73 seconds
Started May 21 12:55:11 PM PDT 24
Finished May 21 12:55:20 PM PDT 24
Peak memory 218588 kb
Host smart-42b6d783-2404-448d-b08f-fc020fa5a74a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146449632 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.kmac_test_vectors_kmac_xof.3146449632 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_224.3580976949
Short name T350
Test name
Test status
Simulation time 19799960571 ps
CPU time 2048.98 seconds
Started May 21 12:55:05 PM PDT 24
Finished May 21 01:29:16 PM PDT 24
Peak memory 388464 kb
Host smart-c1242ee2-4e80-4c99-99d3-3cfec3c8213c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3580976949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_224.3580976949 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_256.1961366104
Short name T520
Test name
Test status
Simulation time 989513315786 ps
CPU time 2134.84 seconds
Started May 21 12:55:11 PM PDT 24
Finished May 21 01:30:48 PM PDT 24
Peak memory 382480 kb
Host smart-ced31f42-5f9c-4440-ab77-3335e7159fb3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1961366104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_256.1961366104 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_384.366110416
Short name T38
Test name
Test status
Simulation time 47487272298 ps
CPU time 1610.97 seconds
Started May 21 12:55:10 PM PDT 24
Finished May 21 01:22:03 PM PDT 24
Peak memory 334812 kb
Host smart-b2561e3f-5ad9-46fe-8e23-a4a4c4882c38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=366110416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_384.366110416 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_512.2845381442
Short name T1050
Test name
Test status
Simulation time 12830549073 ps
CPU time 1154.47 seconds
Started May 21 12:55:11 PM PDT 24
Finished May 21 01:14:28 PM PDT 24
Peak memory 303316 kb
Host smart-03a78f5c-0492-4a4d-84b7-a33b6b644243
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2845381442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_512.2845381442 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_128.1033476850
Short name T420
Test name
Test status
Simulation time 712341488978 ps
CPU time 5894.26 seconds
Started May 21 12:55:11 PM PDT 24
Finished May 21 02:33:28 PM PDT 24
Peak memory 657372 kb
Host smart-ad08cfc1-ade1-45e2-b815-db1c500d83b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1033476850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_128.1033476850 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_256.809835151
Short name T762
Test name
Test status
Simulation time 52144504317 ps
CPU time 4547.4 seconds
Started May 21 12:55:10 PM PDT 24
Finished May 21 02:11:00 PM PDT 24
Peak memory 576572 kb
Host smart-f87a7343-6e7b-442c-bf4f-cd2b580c4cfc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=809835151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_256.809835151 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/28.kmac_alert_test.2132483560
Short name T95
Test name
Test status
Simulation time 64164047 ps
CPU time 0.85 seconds
Started May 21 12:55:34 PM PDT 24
Finished May 21 12:55:37 PM PDT 24
Peak memory 220560 kb
Host smart-409eed11-5c4d-4783-9eca-32553257da76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132483560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.2132483560 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_alert_test/latest

Test location /workspace/coverage/default/28.kmac_app.2972217484
Short name T353
Test name
Test status
Simulation time 17976480239 ps
CPU time 270.68 seconds
Started May 21 12:55:29 PM PDT 24
Finished May 21 01:00:00 PM PDT 24
Peak memory 246212 kb
Host smart-05421660-8d0f-48c9-b9f1-671c96de6efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972217484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.2972217484 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_app/latest

Test location /workspace/coverage/default/28.kmac_burst_write.1792898700
Short name T402
Test name
Test status
Simulation time 15350952728 ps
CPU time 772.15 seconds
Started May 21 12:55:19 PM PDT 24
Finished May 21 01:08:12 PM PDT 24
Peak memory 243068 kb
Host smart-11e95082-93f7-4e1e-b270-c22f064df28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792898700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.1792898700 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_burst_write/latest

Test location /workspace/coverage/default/28.kmac_entropy_refresh.816772714
Short name T995
Test name
Test status
Simulation time 27043428687 ps
CPU time 280.89 seconds
Started May 21 12:55:33 PM PDT 24
Finished May 21 01:00:16 PM PDT 24
Peak memory 247716 kb
Host smart-619088bc-3dce-4eed-a881-31fc3c090750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816772714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.816772714 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/28.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/28.kmac_error.275320744
Short name T534
Test name
Test status
Simulation time 22179673313 ps
CPU time 383.87 seconds
Started May 21 12:55:26 PM PDT 24
Finished May 21 01:01:50 PM PDT 24
Peak memory 267704 kb
Host smart-bc4ebd2d-8462-4c00-994d-041d65ea3f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275320744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.275320744 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_error/latest

Test location /workspace/coverage/default/28.kmac_key_error.687420983
Short name T704
Test name
Test status
Simulation time 3053422497 ps
CPU time 11.55 seconds
Started May 21 12:55:23 PM PDT 24
Finished May 21 12:55:35 PM PDT 24
Peak memory 218524 kb
Host smart-07ad4238-7444-47f8-b57c-4e2abd3550e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687420983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.687420983 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_key_error/latest

Test location /workspace/coverage/default/28.kmac_lc_escalation.2483234116
Short name T299
Test name
Test status
Simulation time 116996251 ps
CPU time 1.34 seconds
Started May 21 12:55:35 PM PDT 24
Finished May 21 12:55:39 PM PDT 24
Peak memory 218676 kb
Host smart-2e35774d-4b94-4e43-9fff-dd3755a256c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483234116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.2483234116 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/28.kmac_lc_escalation/latest

Test location /workspace/coverage/default/28.kmac_long_msg_and_output.3427318358
Short name T501
Test name
Test status
Simulation time 10970000000 ps
CPU time 141.52 seconds
Started May 21 12:55:20 PM PDT 24
Finished May 21 12:57:42 PM PDT 24
Peak memory 240456 kb
Host smart-01c98354-827b-4ae0-9bbe-17d3c688cf6c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427318358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_a
nd_output.3427318358 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/28.kmac_sideload.884184478
Short name T710
Test name
Test status
Simulation time 374724693 ps
CPU time 14.14 seconds
Started May 21 12:55:25 PM PDT 24
Finished May 21 12:55:40 PM PDT 24
Peak memory 230964 kb
Host smart-8dda5636-e722-4e3b-a3fc-7f2b1535eda2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884184478 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.884184478 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_sideload/latest

Test location /workspace/coverage/default/28.kmac_smoke.67830662
Short name T278
Test name
Test status
Simulation time 5124329101 ps
CPU time 27.29 seconds
Started May 21 12:55:17 PM PDT 24
Finished May 21 12:55:45 PM PDT 24
Peak memory 226736 kb
Host smart-5061f076-b882-40a6-8565-cef59e82d217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67830662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.67830662 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_smoke/latest

Test location /workspace/coverage/default/28.kmac_stress_all.865176039
Short name T58
Test name
Test status
Simulation time 30509023476 ps
CPU time 1248.02 seconds
Started May 21 12:55:27 PM PDT 24
Finished May 21 01:16:15 PM PDT 24
Peak memory 341700 kb
Host smart-c4720ccc-fa8f-470f-b3b7-de3742dc3e9b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=865176039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.865176039 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_stress_all/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac.1344996599
Short name T197
Test name
Test status
Simulation time 259693147 ps
CPU time 6.66 seconds
Started May 21 12:55:16 PM PDT 24
Finished May 21 12:55:24 PM PDT 24
Peak memory 219536 kb
Host smart-557343fb-2e55-443c-a076-56a7f891480e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344996599 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.kmac_test_vectors_kmac.1344996599 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac_xof.4189737119
Short name T761
Test name
Test status
Simulation time 125851961 ps
CPU time 6.09 seconds
Started May 21 12:55:25 PM PDT 24
Finished May 21 12:55:32 PM PDT 24
Peak memory 226680 kb
Host smart-6f535980-fac1-4ca8-b6f4-6534d0996184
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189737119 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.kmac_test_vectors_kmac_xof.4189737119 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_224.2481723637
Short name T822
Test name
Test status
Simulation time 141492139695 ps
CPU time 2346.96 seconds
Started May 21 12:55:17 PM PDT 24
Finished May 21 01:34:25 PM PDT 24
Peak memory 408264 kb
Host smart-d84e7fb7-5cc0-452f-a1ea-3c32fe6c2ebc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2481723637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_224.2481723637 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_256.2699338591
Short name T203
Test name
Test status
Simulation time 239797270093 ps
CPU time 1963.58 seconds
Started May 21 12:55:25 PM PDT 24
Finished May 21 01:28:10 PM PDT 24
Peak memory 387688 kb
Host smart-d66463bf-a0e4-4d4c-b2dd-b2ec7edeb09b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2699338591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_256.2699338591 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_384.4062549255
Short name T301
Test name
Test status
Simulation time 15492914475 ps
CPU time 1527.39 seconds
Started May 21 12:55:16 PM PDT 24
Finished May 21 01:20:44 PM PDT 24
Peak memory 342452 kb
Host smart-ed08585c-555a-4220-b74a-0a45c270f1c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4062549255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_384.4062549255 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_512.279994529
Short name T567
Test name
Test status
Simulation time 138078612674 ps
CPU time 1252.6 seconds
Started May 21 12:55:25 PM PDT 24
Finished May 21 01:16:19 PM PDT 24
Peak memory 301876 kb
Host smart-fb2dad68-de22-4c52-a848-d1349e9aef40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=279994529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_512.279994529 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_shake_128.1001057654
Short name T570
Test name
Test status
Simulation time 118589391083 ps
CPU time 5025.41 seconds
Started May 21 12:55:25 PM PDT 24
Finished May 21 02:19:12 PM PDT 24
Peak memory 649612 kb
Host smart-7bbf910b-5bc5-4621-bac2-af5db0b75efc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1001057654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_128.1001057654 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_shake_256.1615426259
Short name T565
Test name
Test status
Simulation time 131585653835 ps
CPU time 4501.84 seconds
Started May 21 12:55:20 PM PDT 24
Finished May 21 02:10:24 PM PDT 24
Peak memory 582236 kb
Host smart-ad4157c6-0d30-4696-b397-43a1e7efd481
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1615426259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_256.1615426259 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/29.kmac_alert_test.993850760
Short name T939
Test name
Test status
Simulation time 29761618 ps
CPU time 0.77 seconds
Started May 21 12:55:38 PM PDT 24
Finished May 21 12:55:41 PM PDT 24
Peak memory 218520 kb
Host smart-722e197e-2516-4e0d-a7a3-1e314a9d092b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993850760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.993850760 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/29.kmac_alert_test/latest

Test location /workspace/coverage/default/29.kmac_app.1743455111
Short name T619
Test name
Test status
Simulation time 10988268150 ps
CPU time 305.65 seconds
Started May 21 12:55:38 PM PDT 24
Finished May 21 01:00:46 PM PDT 24
Peak memory 250680 kb
Host smart-2153eb75-ada6-4e42-8a78-53646584963c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743455111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.1743455111 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_app/latest

Test location /workspace/coverage/default/29.kmac_burst_write.3572206224
Short name T508
Test name
Test status
Simulation time 14151456623 ps
CPU time 1290.21 seconds
Started May 21 12:55:25 PM PDT 24
Finished May 21 01:16:56 PM PDT 24
Peak memory 239344 kb
Host smart-3351caa5-aaaf-494b-a792-5143ad9d8976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572206224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.3572206224 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_burst_write/latest

Test location /workspace/coverage/default/29.kmac_entropy_refresh.3103373946
Short name T529
Test name
Test status
Simulation time 3265142750 ps
CPU time 115.66 seconds
Started May 21 12:55:31 PM PDT 24
Finished May 21 12:57:28 PM PDT 24
Peak memory 234116 kb
Host smart-09ad8700-f8a8-4f13-863f-d15bba9974ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103373946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.3103373946 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/29.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/29.kmac_error.1408694302
Short name T518
Test name
Test status
Simulation time 1929224321 ps
CPU time 129.76 seconds
Started May 21 12:55:39 PM PDT 24
Finished May 21 12:57:50 PM PDT 24
Peak memory 243096 kb
Host smart-cd33bd3e-2d1a-4871-912e-eefe2badbee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408694302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.1408694302 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_error/latest

Test location /workspace/coverage/default/29.kmac_key_error.1472688082
Short name T356
Test name
Test status
Simulation time 5754425011 ps
CPU time 10.27 seconds
Started May 21 12:55:32 PM PDT 24
Finished May 21 12:55:45 PM PDT 24
Peak memory 218528 kb
Host smart-386c6078-dd09-42f3-a37e-0af17ae026b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472688082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.1472688082 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_key_error/latest

Test location /workspace/coverage/default/29.kmac_long_msg_and_output.3577382351
Short name T329
Test name
Test status
Simulation time 112694379786 ps
CPU time 2655.59 seconds
Started May 21 12:55:25 PM PDT 24
Finished May 21 01:39:41 PM PDT 24
Peak memory 460532 kb
Host smart-90e19a10-e19d-4981-9eac-065865afa7ff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577382351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_a
nd_output.3577382351 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/29.kmac_sideload.1722374140
Short name T487
Test name
Test status
Simulation time 171997476155 ps
CPU time 356.15 seconds
Started May 21 12:55:35 PM PDT 24
Finished May 21 01:01:34 PM PDT 24
Peak memory 248132 kb
Host smart-4f424daf-8b55-4ce3-ad7f-14391b1aed87
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722374140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.1722374140 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_sideload/latest

Test location /workspace/coverage/default/29.kmac_smoke.1881366015
Short name T170
Test name
Test status
Simulation time 6815471170 ps
CPU time 53 seconds
Started May 21 12:55:24 PM PDT 24
Finished May 21 12:56:17 PM PDT 24
Peak memory 218656 kb
Host smart-418bec7d-6044-4ea5-aefb-e4e7396298da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881366015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.1881366015 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_smoke/latest

Test location /workspace/coverage/default/29.kmac_stress_all.593202060
Short name T748
Test name
Test status
Simulation time 79299388171 ps
CPU time 755.48 seconds
Started May 21 12:55:31 PM PDT 24
Finished May 21 01:08:08 PM PDT 24
Peak memory 292488 kb
Host smart-064ad4ca-5f1c-469f-aebb-cd77ffec325f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=593202060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.593202060 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_stress_all/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac.3463655449
Short name T791
Test name
Test status
Simulation time 607184315 ps
CPU time 6.44 seconds
Started May 21 12:55:33 PM PDT 24
Finished May 21 12:55:42 PM PDT 24
Peak memory 218612 kb
Host smart-0414a6a8-2810-4da5-bf61-50b22afef330
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463655449 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.kmac_test_vectors_kmac.3463655449 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac_xof.2748865254
Short name T765
Test name
Test status
Simulation time 2561581812 ps
CPU time 6.04 seconds
Started May 21 12:55:31 PM PDT 24
Finished May 21 12:55:38 PM PDT 24
Peak memory 218676 kb
Host smart-d346b786-5f74-40dc-9903-002f81f9da6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748865254 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.kmac_test_vectors_kmac_xof.2748865254 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_224.442163195
Short name T841
Test name
Test status
Simulation time 21736574675 ps
CPU time 2012.9 seconds
Started May 21 12:55:32 PM PDT 24
Finished May 21 01:29:07 PM PDT 24
Peak memory 399208 kb
Host smart-5a3daaff-3cb4-46ef-b835-d5ba7c39a6e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=442163195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_224.442163195 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_256.199375997
Short name T587
Test name
Test status
Simulation time 82434710935 ps
CPU time 1810.43 seconds
Started May 21 12:55:32 PM PDT 24
Finished May 21 01:25:45 PM PDT 24
Peak memory 384208 kb
Host smart-3d89c3f4-496c-425a-a4a3-fb93da09106e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=199375997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_256.199375997 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_384.3750528683
Short name T742
Test name
Test status
Simulation time 846097709386 ps
CPU time 1813.16 seconds
Started May 21 12:55:38 PM PDT 24
Finished May 21 01:25:54 PM PDT 24
Peak memory 333052 kb
Host smart-62d0a5bc-33f6-4854-81c7-602e6a6eef1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3750528683 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_384.3750528683 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_512.499773646
Short name T751
Test name
Test status
Simulation time 167967897480 ps
CPU time 1344.17 seconds
Started May 21 12:55:27 PM PDT 24
Finished May 21 01:17:52 PM PDT 24
Peak memory 299036 kb
Host smart-d8dab031-4b5c-4431-81f6-6a7a2c5b3704
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=499773646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_512.499773646 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_128.2745490694
Short name T636
Test name
Test status
Simulation time 502527969368 ps
CPU time 5794.89 seconds
Started May 21 12:55:30 PM PDT 24
Finished May 21 02:32:06 PM PDT 24
Peak memory 639612 kb
Host smart-bcad4501-a73b-40ea-a2ce-2e25e8585e75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2745490694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_128.2745490694 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_256.2631292641
Short name T867
Test name
Test status
Simulation time 228415306823 ps
CPU time 5178.02 seconds
Started May 21 12:55:33 PM PDT 24
Finished May 21 02:21:54 PM PDT 24
Peak memory 570600 kb
Host smart-931b6d89-7b6e-403a-b5dd-0a14c22a2b17
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2631292641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_256.2631292641 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/3.kmac_alert_test.985491760
Short name T983
Test name
Test status
Simulation time 68445435 ps
CPU time 0.9 seconds
Started May 21 12:53:31 PM PDT 24
Finished May 21 12:53:35 PM PDT 24
Peak memory 218448 kb
Host smart-8045338a-9df0-4954-ad9b-9c9f1d1ad619
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985491760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.985491760 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/3.kmac_alert_test/latest

Test location /workspace/coverage/default/3.kmac_app.2637494530
Short name T728
Test name
Test status
Simulation time 3544335952 ps
CPU time 46.86 seconds
Started May 21 12:53:28 PM PDT 24
Finished May 21 12:54:18 PM PDT 24
Peak memory 227512 kb
Host smart-52ad7e1a-71f7-4f5a-a466-49430c030ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637494530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.2637494530 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_app/latest

Test location /workspace/coverage/default/3.kmac_app_with_partial_data.3716489635
Short name T700
Test name
Test status
Simulation time 420132815 ps
CPU time 12.16 seconds
Started May 21 12:53:31 PM PDT 24
Finished May 21 12:53:46 PM PDT 24
Peak memory 226672 kb
Host smart-7061a7da-2654-4e77-a05e-e841a9589d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716489635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.3716489635 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/3.kmac_burst_write.4202945190
Short name T527
Test name
Test status
Simulation time 99054991704 ps
CPU time 866.29 seconds
Started May 21 12:53:25 PM PDT 24
Finished May 21 01:07:55 PM PDT 24
Peak memory 243096 kb
Host smart-e0a3a3cd-083c-4fdc-9817-f2687fd1a96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202945190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.4202945190 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_burst_write/latest

Test location /workspace/coverage/default/3.kmac_edn_timeout_error.3151090024
Short name T575
Test name
Test status
Simulation time 3827371069 ps
CPU time 16.44 seconds
Started May 21 12:53:47 PM PDT 24
Finished May 21 12:54:07 PM PDT 24
Peak memory 225884 kb
Host smart-78f734e6-d544-431b-aac9-9e5d47cbd94c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3151090024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.3151090024 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_mode_error.1981806460
Short name T406
Test name
Test status
Simulation time 394786108 ps
CPU time 33.55 seconds
Started May 21 12:53:30 PM PDT 24
Finished May 21 12:54:06 PM PDT 24
Peak memory 226908 kb
Host smart-1cedce74-0051-442b-997f-fcfb19682fb9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1981806460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.1981806460 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_ready_error.3007748911
Short name T11
Test name
Test status
Simulation time 8423711525 ps
CPU time 44.48 seconds
Started May 21 12:53:31 PM PDT 24
Finished May 21 12:54:18 PM PDT 24
Peak memory 226720 kb
Host smart-788a8896-68a9-45a5-b46c-45f84e91d345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007748911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.3007748911 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_refresh.4116369538
Short name T964
Test name
Test status
Simulation time 6669700228 ps
CPU time 283.1 seconds
Started May 21 12:53:49 PM PDT 24
Finished May 21 12:58:36 PM PDT 24
Peak memory 246468 kb
Host smart-1cfb4a80-bd65-489f-b7aa-0a64830d6c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116369538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.4116369538 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/3.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/3.kmac_error.3244353064
Short name T528
Test name
Test status
Simulation time 6565397098 ps
CPU time 192.66 seconds
Started May 21 12:53:30 PM PDT 24
Finished May 21 12:56:46 PM PDT 24
Peak memory 251292 kb
Host smart-5dc98ded-41a1-4785-999e-cf81a008cf3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244353064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.3244353064 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_error/latest

Test location /workspace/coverage/default/3.kmac_key_error.391129041
Short name T659
Test name
Test status
Simulation time 1142188309 ps
CPU time 9.05 seconds
Started May 21 12:53:29 PM PDT 24
Finished May 21 12:53:41 PM PDT 24
Peak memory 218496 kb
Host smart-be764431-2eb6-4e57-852c-4b54b0df1908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391129041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.391129041 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_key_error/latest

Test location /workspace/coverage/default/3.kmac_lc_escalation.1586238950
Short name T53
Test name
Test status
Simulation time 92514937 ps
CPU time 1.2 seconds
Started May 21 12:53:40 PM PDT 24
Finished May 21 12:53:44 PM PDT 24
Peak memory 218728 kb
Host smart-919b9fc2-e820-4db4-8f10-2987dee0f66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586238950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.1586238950 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/3.kmac_lc_escalation/latest

Test location /workspace/coverage/default/3.kmac_long_msg_and_output.629785319
Short name T227
Test name
Test status
Simulation time 317462790352 ps
CPU time 1918.23 seconds
Started May 21 12:53:43 PM PDT 24
Finished May 21 01:25:45 PM PDT 24
Peak memory 387108 kb
Host smart-b3ee87eb-1bf8-44a4-af58-3806d0935366
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629785319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_and
_output.629785319 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/3.kmac_mubi.33310825
Short name T515
Test name
Test status
Simulation time 14923260138 ps
CPU time 303.21 seconds
Started May 21 12:53:29 PM PDT 24
Finished May 21 12:58:36 PM PDT 24
Peak memory 247788 kb
Host smart-f8fcd878-cb1b-4a5a-8b8a-dd8b5a5536b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33310825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.33310825 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mubi/latest

Test location /workspace/coverage/default/3.kmac_sec_cm.163476468
Short name T32
Test name
Test status
Simulation time 3464598227 ps
CPU time 48.57 seconds
Started May 21 12:53:54 PM PDT 24
Finished May 21 12:54:47 PM PDT 24
Peak memory 256852 kb
Host smart-aa8b34d4-9d89-4fe8-a425-696b3aa08588
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163476468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.163476468 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/3.kmac_sec_cm/latest

Test location /workspace/coverage/default/3.kmac_sideload.2490365536
Short name T962
Test name
Test status
Simulation time 9944661484 ps
CPU time 303.83 seconds
Started May 21 12:53:22 PM PDT 24
Finished May 21 12:58:31 PM PDT 24
Peak memory 247208 kb
Host smart-a34dec00-77e5-44cd-996d-dd914cb354e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490365536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.2490365536 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_sideload/latest

Test location /workspace/coverage/default/3.kmac_smoke.3608413032
Short name T199
Test name
Test status
Simulation time 7563981395 ps
CPU time 54.59 seconds
Started May 21 12:53:21 PM PDT 24
Finished May 21 12:54:20 PM PDT 24
Peak memory 222696 kb
Host smart-2e59b1b3-04cc-4047-b9b1-bb4f613bd97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608413032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.3608413032 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_smoke/latest

Test location /workspace/coverage/default/3.kmac_stress_all.2625986993
Short name T108
Test name
Test status
Simulation time 65626819953 ps
CPU time 668.22 seconds
Started May 21 12:53:41 PM PDT 24
Finished May 21 01:04:51 PM PDT 24
Peak memory 284448 kb
Host smart-ef4885a4-81af-4c59-a7b2-a3a8e1e8a4a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2625986993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.2625986993 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_stress_all/latest

Test location /workspace/coverage/default/3.kmac_stress_all_with_rand_reset.3714276949
Short name T119
Test name
Test status
Simulation time 11706045393 ps
CPU time 717.01 seconds
Started May 21 12:53:45 PM PDT 24
Finished May 21 01:05:45 PM PDT 24
Peak memory 308964 kb
Host smart-4b6e3cea-0908-4b44-a628-8f9dd19d51de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3714276949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all_with_rand_reset.3714276949 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac.3372501884
Short name T1022
Test name
Test status
Simulation time 1059410449 ps
CPU time 6.69 seconds
Started May 21 12:53:27 PM PDT 24
Finished May 21 12:53:37 PM PDT 24
Peak memory 226436 kb
Host smart-ecc7933b-cbcd-40a4-becc-d06dd7d7a156
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372501884 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.kmac_test_vectors_kmac.3372501884 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac_xof.2931595260
Short name T358
Test name
Test status
Simulation time 108233827 ps
CPU time 5.67 seconds
Started May 21 12:53:30 PM PDT 24
Finished May 21 12:53:39 PM PDT 24
Peak memory 218636 kb
Host smart-c8bfa698-1e50-49d7-a5e8-454c4a85008e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931595260 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.kmac_test_vectors_kmac_xof.2931595260 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_224.3874989187
Short name T690
Test name
Test status
Simulation time 107752697458 ps
CPU time 1978.7 seconds
Started May 21 12:53:21 PM PDT 24
Finished May 21 01:26:24 PM PDT 24
Peak memory 393472 kb
Host smart-c3651c33-be22-4909-bbd0-d82ce573fb83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3874989187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.3874989187 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_256.3769295373
Short name T1043
Test name
Test status
Simulation time 805438661179 ps
CPU time 2347.54 seconds
Started May 21 12:53:38 PM PDT 24
Finished May 21 01:32:48 PM PDT 24
Peak memory 387296 kb
Host smart-6b8afa46-1cd0-4555-b198-b98224a19bc5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3769295373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.3769295373 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_384.1838506700
Short name T568
Test name
Test status
Simulation time 14850917484 ps
CPU time 1475.62 seconds
Started May 21 12:53:45 PM PDT 24
Finished May 21 01:18:24 PM PDT 24
Peak memory 338464 kb
Host smart-29df0a3e-1db6-424c-a036-1f9160adcba3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1838506700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.1838506700 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_512.3810412469
Short name T453
Test name
Test status
Simulation time 68272645464 ps
CPU time 1291.12 seconds
Started May 21 12:53:22 PM PDT 24
Finished May 21 01:14:58 PM PDT 24
Peak memory 300996 kb
Host smart-cad82a74-6863-4d55-8782-7d0e46b152ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3810412469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.3810412469 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_128.2194537887
Short name T990
Test name
Test status
Simulation time 61149641718 ps
CPU time 5031.02 seconds
Started May 21 12:53:26 PM PDT 24
Finished May 21 02:17:21 PM PDT 24
Peak memory 665104 kb
Host smart-cb157678-93c1-43ce-9f72-ff42c9cc438b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2194537887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.2194537887 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_256.4165397733
Short name T1046
Test name
Test status
Simulation time 796358555305 ps
CPU time 5017.24 seconds
Started May 21 12:53:20 PM PDT 24
Finished May 21 02:17:03 PM PDT 24
Peak memory 566968 kb
Host smart-20fe0815-ac21-44b6-b5c6-cf05353fb57e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4165397733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.4165397733 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/30.kmac_alert_test.2828635249
Short name T769
Test name
Test status
Simulation time 17231878 ps
CPU time 0.87 seconds
Started May 21 12:55:36 PM PDT 24
Finished May 21 12:55:39 PM PDT 24
Peak memory 218472 kb
Host smart-834c1eaf-8ad2-4baa-aa2d-67140003c183
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828635249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.2828635249 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_alert_test/latest

Test location /workspace/coverage/default/30.kmac_app.2260961338
Short name T217
Test name
Test status
Simulation time 29007657704 ps
CPU time 390.31 seconds
Started May 21 12:55:37 PM PDT 24
Finished May 21 01:02:09 PM PDT 24
Peak memory 252648 kb
Host smart-12d54863-253c-43a3-a7ed-aca028ebadbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260961338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.2260961338 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_app/latest

Test location /workspace/coverage/default/30.kmac_burst_write.3622368081
Short name T624
Test name
Test status
Simulation time 27402338163 ps
CPU time 687.48 seconds
Started May 21 12:55:39 PM PDT 24
Finished May 21 01:07:09 PM PDT 24
Peak memory 235580 kb
Host smart-c0ec1440-ab1a-4cb7-8f6e-7f807f7770ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622368081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.3622368081 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_burst_write/latest

Test location /workspace/coverage/default/30.kmac_entropy_refresh.993012267
Short name T250
Test name
Test status
Simulation time 15209563028 ps
CPU time 92.02 seconds
Started May 21 12:55:35 PM PDT 24
Finished May 21 12:57:09 PM PDT 24
Peak memory 241108 kb
Host smart-52038ada-e01d-443c-a932-a1d0d6e503b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993012267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.993012267 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/30.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/30.kmac_error.4053885450
Short name T21
Test name
Test status
Simulation time 4014255225 ps
CPU time 104.19 seconds
Started May 21 12:55:39 PM PDT 24
Finished May 21 12:57:25 PM PDT 24
Peak memory 243732 kb
Host smart-2baba732-0e17-462a-ae1c-de0626157326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053885450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.4053885450 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_error/latest

Test location /workspace/coverage/default/30.kmac_key_error.4000676050
Short name T422
Test name
Test status
Simulation time 2246248971 ps
CPU time 9.87 seconds
Started May 21 12:55:36 PM PDT 24
Finished May 21 12:55:48 PM PDT 24
Peak memory 218540 kb
Host smart-270ccbb4-eef6-4bae-94d8-a24c8d1223b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000676050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.4000676050 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_key_error/latest

Test location /workspace/coverage/default/30.kmac_long_msg_and_output.974228412
Short name T673
Test name
Test status
Simulation time 97686390911 ps
CPU time 1232.15 seconds
Started May 21 12:55:33 PM PDT 24
Finished May 21 01:16:08 PM PDT 24
Peak memory 331780 kb
Host smart-46e621ae-514b-46b3-b90b-aca3c194c307
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974228412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_an
d_output.974228412 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/30.kmac_sideload.3328457901
Short name T256
Test name
Test status
Simulation time 32667991952 ps
CPU time 459 seconds
Started May 21 12:55:33 PM PDT 24
Finished May 21 01:03:14 PM PDT 24
Peak memory 256208 kb
Host smart-4c57331f-b085-4b8e-80a0-ea1717c4ee70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328457901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.3328457901 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_sideload/latest

Test location /workspace/coverage/default/30.kmac_smoke.2022891519
Short name T976
Test name
Test status
Simulation time 86073208 ps
CPU time 3.13 seconds
Started May 21 12:55:33 PM PDT 24
Finished May 21 12:55:38 PM PDT 24
Peak memory 218592 kb
Host smart-7a83b17a-8fc5-47d5-86ae-9c0a505880e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022891519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.2022891519 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_smoke/latest

Test location /workspace/coverage/default/30.kmac_stress_all.2623051130
Short name T423
Test name
Test status
Simulation time 62978459631 ps
CPU time 863.39 seconds
Started May 21 12:55:36 PM PDT 24
Finished May 21 01:10:01 PM PDT 24
Peak memory 317972 kb
Host smart-eb18647c-448a-422e-b62a-b56c6a949999
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2623051130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.2623051130 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_stress_all/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac.4212428979
Short name T782
Test name
Test status
Simulation time 266943928 ps
CPU time 6.47 seconds
Started May 21 12:55:39 PM PDT 24
Finished May 21 12:55:48 PM PDT 24
Peak memory 226640 kb
Host smart-b32579a3-50b6-497d-85d5-f04e7ec95fa1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212428979 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.kmac_test_vectors_kmac.4212428979 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac_xof.2480674007
Short name T878
Test name
Test status
Simulation time 423555472 ps
CPU time 5.86 seconds
Started May 21 12:55:37 PM PDT 24
Finished May 21 12:55:45 PM PDT 24
Peak memory 219600 kb
Host smart-83073c23-48c1-485d-b5b6-4ca66f6c737a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480674007 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.kmac_test_vectors_kmac_xof.2480674007 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_224.2130592078
Short name T195
Test name
Test status
Simulation time 322867787810 ps
CPU time 2188.21 seconds
Started May 21 12:55:30 PM PDT 24
Finished May 21 01:31:59 PM PDT 24
Peak memory 404788 kb
Host smart-79a145d4-6411-4c94-bde9-6ce2e6a881dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2130592078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_224.2130592078 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_256.3919231898
Short name T644
Test name
Test status
Simulation time 197223557040 ps
CPU time 2107.9 seconds
Started May 21 12:55:30 PM PDT 24
Finished May 21 01:30:39 PM PDT 24
Peak memory 382628 kb
Host smart-4b939346-f80d-4fbc-bf45-5f79144fe996
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3919231898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_256.3919231898 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_384.2162692102
Short name T317
Test name
Test status
Simulation time 58806266559 ps
CPU time 1542.4 seconds
Started May 21 12:55:31 PM PDT 24
Finished May 21 01:21:16 PM PDT 24
Peak memory 337336 kb
Host smart-c5604f99-e977-4b0c-8136-441c8adf4bfd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2162692102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_384.2162692102 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_512.3598784669
Short name T1070
Test name
Test status
Simulation time 21503969449 ps
CPU time 1153.15 seconds
Started May 21 12:55:33 PM PDT 24
Finished May 21 01:14:49 PM PDT 24
Peak memory 296396 kb
Host smart-971abe0e-8537-4eb8-ade6-91e70627e0da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3598784669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_512.3598784669 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_128.4074031674
Short name T187
Test name
Test status
Simulation time 60426460315 ps
CPU time 5072.02 seconds
Started May 21 12:55:31 PM PDT 24
Finished May 21 02:20:06 PM PDT 24
Peak memory 662996 kb
Host smart-4ac3428d-5403-4722-95c1-5e0b77492217
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4074031674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_128.4074031674 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_256.3879528934
Short name T251
Test name
Test status
Simulation time 114282192801 ps
CPU time 4287.69 seconds
Started May 21 12:55:35 PM PDT 24
Finished May 21 02:07:05 PM PDT 24
Peak memory 564340 kb
Host smart-cecaa03e-56ba-4485-a869-60e559dfb578
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3879528934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_256.3879528934 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/31.kmac_alert_test.3268379826
Short name T895
Test name
Test status
Simulation time 30203751 ps
CPU time 0.86 seconds
Started May 21 12:55:48 PM PDT 24
Finished May 21 12:55:49 PM PDT 24
Peak memory 218512 kb
Host smart-a5bd6a1a-4085-42ac-b064-cf95ef55903d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268379826 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.3268379826 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_alert_test/latest

Test location /workspace/coverage/default/31.kmac_app.3480789781
Short name T205
Test name
Test status
Simulation time 13412584007 ps
CPU time 89.06 seconds
Started May 21 12:55:49 PM PDT 24
Finished May 21 12:57:19 PM PDT 24
Peak memory 231608 kb
Host smart-e68e3268-7002-4d7b-8ccd-9ad176252d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480789781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.3480789781 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_app/latest

Test location /workspace/coverage/default/31.kmac_burst_write.852049301
Short name T842
Test name
Test status
Simulation time 5597389744 ps
CPU time 538.32 seconds
Started May 21 12:55:39 PM PDT 24
Finished May 21 01:04:39 PM PDT 24
Peak memory 242272 kb
Host smart-833e846b-8652-4604-8a06-e5ebd043f295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852049301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.852049301 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_burst_write/latest

Test location /workspace/coverage/default/31.kmac_entropy_refresh.1568885285
Short name T206
Test name
Test status
Simulation time 7025255897 ps
CPU time 286.72 seconds
Started May 21 12:55:46 PM PDT 24
Finished May 21 01:00:34 PM PDT 24
Peak memory 247016 kb
Host smart-7476db27-788c-4d4d-8c7e-d7190c1d721c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568885285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.1568885285 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/31.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/31.kmac_error.1305791866
Short name T414
Test name
Test status
Simulation time 17125227788 ps
CPU time 317.93 seconds
Started May 21 12:55:48 PM PDT 24
Finished May 21 01:01:07 PM PDT 24
Peak memory 253392 kb
Host smart-764ed1f0-279e-4f9c-b5de-2c3029990e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305791866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.1305791866 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_error/latest

Test location /workspace/coverage/default/31.kmac_key_error.1701111319
Short name T548
Test name
Test status
Simulation time 1261169058 ps
CPU time 8.11 seconds
Started May 21 12:55:49 PM PDT 24
Finished May 21 12:55:57 PM PDT 24
Peak memory 218452 kb
Host smart-652ef926-d074-4f3c-b3f4-fa2f9cccb579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701111319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.1701111319 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_key_error/latest

Test location /workspace/coverage/default/31.kmac_lc_escalation.133837694
Short name T660
Test name
Test status
Simulation time 1024390842 ps
CPU time 22.33 seconds
Started May 21 12:55:46 PM PDT 24
Finished May 21 12:56:10 PM PDT 24
Peak memory 233292 kb
Host smart-fd73cffb-0a42-458e-931e-0ca5648fda4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133837694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.133837694 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/31.kmac_lc_escalation/latest

Test location /workspace/coverage/default/31.kmac_long_msg_and_output.1494016652
Short name T104
Test name
Test status
Simulation time 426027633 ps
CPU time 45.64 seconds
Started May 21 12:55:37 PM PDT 24
Finished May 21 12:56:25 PM PDT 24
Peak memory 222200 kb
Host smart-cb789919-e767-4045-9ea6-16a991cf56b9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494016652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_a
nd_output.1494016652 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/31.kmac_sideload.3899088949
Short name T232
Test name
Test status
Simulation time 494460249 ps
CPU time 12.77 seconds
Started May 21 12:55:36 PM PDT 24
Finished May 21 12:55:51 PM PDT 24
Peak memory 226664 kb
Host smart-dd7edec3-8793-4a69-8703-1e2f91eb2829
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899088949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.3899088949 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_sideload/latest

Test location /workspace/coverage/default/31.kmac_smoke.396063640
Short name T714
Test name
Test status
Simulation time 20564221924 ps
CPU time 95.04 seconds
Started May 21 12:55:37 PM PDT 24
Finished May 21 12:57:14 PM PDT 24
Peak memory 226760 kb
Host smart-cb3173f2-4613-4327-98ea-7c5cae308f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396063640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.396063640 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_smoke/latest

Test location /workspace/coverage/default/31.kmac_stress_all.1345185924
Short name T122
Test name
Test status
Simulation time 43282983207 ps
CPU time 643.5 seconds
Started May 21 12:55:51 PM PDT 24
Finished May 21 01:06:35 PM PDT 24
Peak memory 269876 kb
Host smart-b61a56a5-7380-484f-93a0-b1ee45c3075e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1345185924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.1345185924 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_stress_all/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac.3255239601
Short name T796
Test name
Test status
Simulation time 799626205 ps
CPU time 5.94 seconds
Started May 21 12:55:42 PM PDT 24
Finished May 21 12:55:50 PM PDT 24
Peak memory 226636 kb
Host smart-b34f7365-b257-4b6a-9e90-568835b0b3b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255239601 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.kmac_test_vectors_kmac.3255239601 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac_xof.2991793033
Short name T274
Test name
Test status
Simulation time 193143783 ps
CPU time 6.01 seconds
Started May 21 12:55:43 PM PDT 24
Finished May 21 12:55:51 PM PDT 24
Peak memory 226696 kb
Host smart-84cc6958-f555-4770-98ca-b3d92c8ae974
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991793033 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.kmac_test_vectors_kmac_xof.2991793033 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_224.3361294460
Short name T456
Test name
Test status
Simulation time 28227412028 ps
CPU time 2053.12 seconds
Started May 21 12:55:42 PM PDT 24
Finished May 21 01:29:58 PM PDT 24
Peak memory 407052 kb
Host smart-3b0dfec8-b636-42ed-9f97-f794109d3207
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3361294460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_224.3361294460 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_256.3486297499
Short name T837
Test name
Test status
Simulation time 159000283937 ps
CPU time 1834.13 seconds
Started May 21 12:55:43 PM PDT 24
Finished May 21 01:26:19 PM PDT 24
Peak memory 383556 kb
Host smart-f72efd18-cf12-48fc-98c9-a00b77489953
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3486297499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_256.3486297499 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_384.1547257844
Short name T179
Test name
Test status
Simulation time 21850367211 ps
CPU time 1572.12 seconds
Started May 21 12:55:45 PM PDT 24
Finished May 21 01:21:58 PM PDT 24
Peak memory 337044 kb
Host smart-bc9fb172-0ff7-4f7c-9747-cd2cb5df363a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1547257844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_384.1547257844 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_512.1681682324
Short name T427
Test name
Test status
Simulation time 70038903904 ps
CPU time 1340.84 seconds
Started May 21 12:55:44 PM PDT 24
Finished May 21 01:18:06 PM PDT 24
Peak memory 298076 kb
Host smart-096e9951-fac3-407e-a0f7-e9ee100492d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1681682324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_512.1681682324 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_shake_128.1740825344
Short name T266
Test name
Test status
Simulation time 239122155986 ps
CPU time 5061.11 seconds
Started May 21 12:55:43 PM PDT 24
Finished May 21 02:20:06 PM PDT 24
Peak memory 649580 kb
Host smart-42a9d552-1836-458c-bd71-46be58fa058f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1740825344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_128.1740825344 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_shake_256.2674338557
Short name T416
Test name
Test status
Simulation time 54715025191 ps
CPU time 4500.85 seconds
Started May 21 12:55:42 PM PDT 24
Finished May 21 02:10:46 PM PDT 24
Peak memory 574552 kb
Host smart-a7a37b44-a16f-4a3e-96e4-2cb751799640
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2674338557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_256.2674338557 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/32.kmac_alert_test.2637692800
Short name T1065
Test name
Test status
Simulation time 93908107 ps
CPU time 0.95 seconds
Started May 21 12:56:00 PM PDT 24
Finished May 21 12:56:01 PM PDT 24
Peak memory 218524 kb
Host smart-417bbb3a-0613-4f80-ba74-682ad8aa563c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637692800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.2637692800 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_alert_test/latest

Test location /workspace/coverage/default/32.kmac_app.1821697945
Short name T340
Test name
Test status
Simulation time 8121549437 ps
CPU time 228.11 seconds
Started May 21 12:55:54 PM PDT 24
Finished May 21 12:59:43 PM PDT 24
Peak memory 244456 kb
Host smart-360c1134-27b9-455d-bc61-d7b8dd329480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821697945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.1821697945 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_app/latest

Test location /workspace/coverage/default/32.kmac_burst_write.3215173372
Short name T1019
Test name
Test status
Simulation time 25803973799 ps
CPU time 1163.96 seconds
Started May 21 12:55:52 PM PDT 24
Finished May 21 01:15:16 PM PDT 24
Peak memory 236844 kb
Host smart-0060e015-cbf2-4024-8303-ba27ecdc4cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215173372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.3215173372 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_burst_write/latest

Test location /workspace/coverage/default/32.kmac_entropy_refresh.1250121564
Short name T611
Test name
Test status
Simulation time 6798828355 ps
CPU time 145.62 seconds
Started May 21 12:55:59 PM PDT 24
Finished May 21 12:58:26 PM PDT 24
Peak memory 237116 kb
Host smart-19b6149a-dc55-470d-b215-a73805cc0463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250121564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.1250121564 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/32.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/32.kmac_error.3590733096
Short name T745
Test name
Test status
Simulation time 4181355021 ps
CPU time 25.01 seconds
Started May 21 12:56:00 PM PDT 24
Finished May 21 12:56:26 PM PDT 24
Peak memory 240328 kb
Host smart-5a9fe19b-d0a1-43cd-b3a2-68ed0a3e0993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590733096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.3590733096 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_error/latest

Test location /workspace/coverage/default/32.kmac_key_error.1178912187
Short name T744
Test name
Test status
Simulation time 2143235181 ps
CPU time 13.33 seconds
Started May 21 12:56:00 PM PDT 24
Finished May 21 12:56:14 PM PDT 24
Peak memory 218496 kb
Host smart-861ded34-1a78-4114-9371-d587ea72d45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178912187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.1178912187 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_key_error/latest

Test location /workspace/coverage/default/32.kmac_lc_escalation.3561742727
Short name T560
Test name
Test status
Simulation time 36523851 ps
CPU time 1.44 seconds
Started May 21 12:56:02 PM PDT 24
Finished May 21 12:56:04 PM PDT 24
Peak memory 218844 kb
Host smart-65b4bf1e-bcc1-4e2f-a6d4-a39ec86dad35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561742727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.3561742727 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/32.kmac_lc_escalation/latest

Test location /workspace/coverage/default/32.kmac_sideload.3070342892
Short name T1003
Test name
Test status
Simulation time 27901155343 ps
CPU time 303.87 seconds
Started May 21 12:55:49 PM PDT 24
Finished May 21 01:00:54 PM PDT 24
Peak memory 244608 kb
Host smart-2b18602a-cb09-4c5f-96de-f4a45515c9cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070342892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.3070342892 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_sideload/latest

Test location /workspace/coverage/default/32.kmac_smoke.3803846029
Short name T654
Test name
Test status
Simulation time 29086438536 ps
CPU time 49.63 seconds
Started May 21 12:55:51 PM PDT 24
Finished May 21 12:56:41 PM PDT 24
Peak memory 226764 kb
Host smart-0e38c10c-0af6-4c7c-8215-0e7caadabc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803846029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.3803846029 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_smoke/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac.3566200291
Short name T1026
Test name
Test status
Simulation time 298301102 ps
CPU time 7.33 seconds
Started May 21 12:55:56 PM PDT 24
Finished May 21 12:56:04 PM PDT 24
Peak memory 218676 kb
Host smart-16144c20-c00d-4a5e-adcc-e34e0e56c5b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566200291 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.kmac_test_vectors_kmac.3566200291 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac_xof.456541193
Short name T143
Test name
Test status
Simulation time 260842545 ps
CPU time 6.8 seconds
Started May 21 12:55:55 PM PDT 24
Finished May 21 12:56:03 PM PDT 24
Peak memory 218632 kb
Host smart-6a633688-b80b-476c-8e7d-6a27c3d0cfc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456541193 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.kmac_test_vectors_kmac_xof.456541193 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_224.847416717
Short name T828
Test name
Test status
Simulation time 337043232484 ps
CPU time 2034.04 seconds
Started May 21 12:55:51 PM PDT 24
Finished May 21 01:29:46 PM PDT 24
Peak memory 381744 kb
Host smart-c4e381cd-74f3-4c47-bbc8-b7a35b90fdd5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=847416717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_224.847416717 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_256.3225125119
Short name T1041
Test name
Test status
Simulation time 92147171773 ps
CPU time 2333.28 seconds
Started May 21 12:55:47 PM PDT 24
Finished May 21 01:34:41 PM PDT 24
Peak memory 385128 kb
Host smart-3e175cbc-ac61-4b17-a3c1-d1ca4dc1eaa5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3225125119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_256.3225125119 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_384.3738477623
Short name T639
Test name
Test status
Simulation time 61521696975 ps
CPU time 1399.85 seconds
Started May 21 12:55:55 PM PDT 24
Finished May 21 01:19:16 PM PDT 24
Peak memory 338892 kb
Host smart-1bef824f-67ab-4c6f-96df-24ce34d044d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3738477623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_384.3738477623 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_512.1855829457
Short name T221
Test name
Test status
Simulation time 90029660866 ps
CPU time 1235.44 seconds
Started May 21 12:55:56 PM PDT 24
Finished May 21 01:16:32 PM PDT 24
Peak memory 301916 kb
Host smart-c014df76-0687-4087-b1b6-19b76211a03a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1855829457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_512.1855829457 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_128.3104418121
Short name T869
Test name
Test status
Simulation time 1086011001849 ps
CPU time 5958.63 seconds
Started May 21 12:55:54 PM PDT 24
Finished May 21 02:35:14 PM PDT 24
Peak memory 659388 kb
Host smart-6937b613-9d3a-417c-86c0-6d26599d4a90
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3104418121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_128.3104418121 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_256.927510621
Short name T886
Test name
Test status
Simulation time 609701003481 ps
CPU time 4740.04 seconds
Started May 21 12:55:53 PM PDT 24
Finished May 21 02:14:54 PM PDT 24
Peak memory 572668 kb
Host smart-262ca06f-03ba-4c39-8b76-9ebc44d85785
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=927510621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_256.927510621 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/33.kmac_alert_test.607315681
Short name T36
Test name
Test status
Simulation time 18973103 ps
CPU time 0.86 seconds
Started May 21 12:56:13 PM PDT 24
Finished May 21 12:56:15 PM PDT 24
Peak memory 218516 kb
Host smart-e205400c-4d41-47a6-ac69-c9895d68575d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607315681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.607315681 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/33.kmac_alert_test/latest

Test location /workspace/coverage/default/33.kmac_app.2347198086
Short name T502
Test name
Test status
Simulation time 11815765023 ps
CPU time 270.07 seconds
Started May 21 12:56:14 PM PDT 24
Finished May 21 01:00:45 PM PDT 24
Peak memory 245844 kb
Host smart-89c8a2db-70ce-4c82-947c-c4cc5cb69663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347198086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.2347198086 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_app/latest

Test location /workspace/coverage/default/33.kmac_burst_write.4218830087
Short name T328
Test name
Test status
Simulation time 32289693482 ps
CPU time 1089.39 seconds
Started May 21 12:56:02 PM PDT 24
Finished May 21 01:14:12 PM PDT 24
Peak memory 238512 kb
Host smart-af723871-0eba-4fbd-b6f7-dbdab2c1ae49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218830087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.4218830087 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_burst_write/latest

Test location /workspace/coverage/default/33.kmac_entropy_refresh.1541945881
Short name T71
Test name
Test status
Simulation time 18195920604 ps
CPU time 292.73 seconds
Started May 21 12:56:14 PM PDT 24
Finished May 21 01:01:08 PM PDT 24
Peak memory 248852 kb
Host smart-3078bc54-5369-4e71-bd31-938fffedeeeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541945881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.1541945881 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/33.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/33.kmac_error.55141395
Short name T24
Test name
Test status
Simulation time 3859724900 ps
CPU time 349.6 seconds
Started May 21 12:56:14 PM PDT 24
Finished May 21 01:02:05 PM PDT 24
Peak memory 259476 kb
Host smart-5af5a218-3abc-4180-84e5-9c993cd6619a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55141395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.55141395 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_error/latest

Test location /workspace/coverage/default/33.kmac_key_error.1679732588
Short name T598
Test name
Test status
Simulation time 1259513607 ps
CPU time 10.52 seconds
Started May 21 12:56:14 PM PDT 24
Finished May 21 12:56:26 PM PDT 24
Peak memory 218376 kb
Host smart-7832dd36-2887-4fcc-af48-108133b0f287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679732588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.1679732588 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_key_error/latest

Test location /workspace/coverage/default/33.kmac_lc_escalation.1504560983
Short name T787
Test name
Test status
Simulation time 337361630 ps
CPU time 1.4 seconds
Started May 21 12:56:14 PM PDT 24
Finished May 21 12:56:17 PM PDT 24
Peak memory 218664 kb
Host smart-12ec930a-239a-40d4-a1de-72672ada0510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504560983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.1504560983 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/33.kmac_lc_escalation/latest

Test location /workspace/coverage/default/33.kmac_long_msg_and_output.1461523169
Short name T618
Test name
Test status
Simulation time 16324916432 ps
CPU time 394.53 seconds
Started May 21 12:56:01 PM PDT 24
Finished May 21 01:02:37 PM PDT 24
Peak memory 260720 kb
Host smart-93b0fe43-393a-4223-9f0d-d90f3e56bd19
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461523169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_a
nd_output.1461523169 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/33.kmac_sideload.736204294
Short name T781
Test name
Test status
Simulation time 29425183961 ps
CPU time 495.3 seconds
Started May 21 12:56:00 PM PDT 24
Finished May 21 01:04:16 PM PDT 24
Peak memory 256324 kb
Host smart-30c1644b-be51-4f74-8134-2805ce9d9ffa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736204294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.736204294 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_sideload/latest

Test location /workspace/coverage/default/33.kmac_smoke.2970368879
Short name T1066
Test name
Test status
Simulation time 653694087 ps
CPU time 25.14 seconds
Started May 21 12:56:02 PM PDT 24
Finished May 21 12:56:28 PM PDT 24
Peak memory 223388 kb
Host smart-023fe7b7-a17a-4a58-afaa-d7e9009022e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970368879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.2970368879 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_smoke/latest

Test location /workspace/coverage/default/33.kmac_stress_all.3343271743
Short name T399
Test name
Test status
Simulation time 40530613773 ps
CPU time 1320.91 seconds
Started May 21 12:56:13 PM PDT 24
Finished May 21 01:18:15 PM PDT 24
Peak memory 349856 kb
Host smart-3dadc11f-486c-4b19-b930-07644c2a006f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3343271743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.3343271743 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_stress_all/latest

Test location /workspace/coverage/default/33.kmac_stress_all_with_rand_reset.2034534193
Short name T121
Test name
Test status
Simulation time 113963390536 ps
CPU time 1171.46 seconds
Started May 21 12:56:13 PM PDT 24
Finished May 21 01:15:46 PM PDT 24
Peak memory 292680 kb
Host smart-79540038-393c-45ff-b259-25882937fbf5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2034534193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all_with_rand_reset.2034534193 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac.627046961
Short name T935
Test name
Test status
Simulation time 668421307 ps
CPU time 6.36 seconds
Started May 21 12:56:14 PM PDT 24
Finished May 21 12:56:22 PM PDT 24
Peak memory 219536 kb
Host smart-e08bb22c-bf29-4273-83d6-83401e4cf2f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627046961 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.kmac_test_vectors_kmac.627046961 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac_xof.1125910607
Short name T671
Test name
Test status
Simulation time 1176414377 ps
CPU time 6.23 seconds
Started May 21 12:56:14 PM PDT 24
Finished May 21 12:56:21 PM PDT 24
Peak memory 226676 kb
Host smart-8ccac07b-8e9e-4395-871f-d7125cdc9fdc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125910607 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.kmac_test_vectors_kmac_xof.1125910607 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_224.1026304387
Short name T193
Test name
Test status
Simulation time 21148763904 ps
CPU time 2088.62 seconds
Started May 21 12:56:08 PM PDT 24
Finished May 21 01:30:57 PM PDT 24
Peak memory 396028 kb
Host smart-bb660beb-1942-4eab-8c76-01daaf911095
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1026304387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_224.1026304387 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_256.305886596
Short name T612
Test name
Test status
Simulation time 194495532793 ps
CPU time 2337.4 seconds
Started May 21 12:56:08 PM PDT 24
Finished May 21 01:35:07 PM PDT 24
Peak memory 393828 kb
Host smart-d7d50d0a-62b7-4f24-bf05-4e24f0c46d8a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=305886596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_256.305886596 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_384.1450962586
Short name T832
Test name
Test status
Simulation time 49671119525 ps
CPU time 1623.6 seconds
Started May 21 12:56:09 PM PDT 24
Finished May 21 01:23:13 PM PDT 24
Peak memory 341736 kb
Host smart-72f7eea1-36d1-49c2-a20b-612b36e3dc92
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1450962586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_384.1450962586 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_512.2225902547
Short name T252
Test name
Test status
Simulation time 45873019786 ps
CPU time 1242.79 seconds
Started May 21 12:56:09 PM PDT 24
Finished May 21 01:16:52 PM PDT 24
Peak memory 300080 kb
Host smart-9f75a8d6-3d72-47bb-bc9a-3b95861ae3d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2225902547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_512.2225902547 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_shake_128.3273360448
Short name T383
Test name
Test status
Simulation time 372784614512 ps
CPU time 6050.63 seconds
Started May 21 12:56:08 PM PDT 24
Finished May 21 02:36:59 PM PDT 24
Peak memory 659676 kb
Host smart-7d92a396-66fa-4ac5-b497-7983620f2585
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3273360448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_128.3273360448 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_shake_256.1604939318
Short name T245
Test name
Test status
Simulation time 110152752477 ps
CPU time 4366.28 seconds
Started May 21 12:56:13 PM PDT 24
Finished May 21 02:09:01 PM PDT 24
Peak memory 571024 kb
Host smart-36a4c668-0db0-4ef3-bed4-bbad90bbd7d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1604939318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_256.1604939318 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/34.kmac_alert_test.3735380981
Short name T264
Test name
Test status
Simulation time 22763026 ps
CPU time 0.82 seconds
Started May 21 12:56:21 PM PDT 24
Finished May 21 12:56:22 PM PDT 24
Peak memory 218508 kb
Host smart-de6cc827-dd91-414d-887d-fd29071288c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735380981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.3735380981 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_alert_test/latest

Test location /workspace/coverage/default/34.kmac_app.1898381363
Short name T634
Test name
Test status
Simulation time 5170234590 ps
CPU time 309.5 seconds
Started May 21 12:56:19 PM PDT 24
Finished May 21 01:01:30 PM PDT 24
Peak memory 250188 kb
Host smart-93a3127a-70f9-4c18-b459-e50c065419da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898381363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.1898381363 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_app/latest

Test location /workspace/coverage/default/34.kmac_burst_write.1086756272
Short name T279
Test name
Test status
Simulation time 30138728726 ps
CPU time 1085.79 seconds
Started May 21 12:56:14 PM PDT 24
Finished May 21 01:14:21 PM PDT 24
Peak memory 237508 kb
Host smart-95d3b130-e1db-465a-bb4d-d90e5673abfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086756272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.1086756272 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_burst_write/latest

Test location /workspace/coverage/default/34.kmac_entropy_refresh.3589380896
Short name T1023
Test name
Test status
Simulation time 43762371345 ps
CPU time 258.56 seconds
Started May 21 12:56:21 PM PDT 24
Finished May 21 01:00:40 PM PDT 24
Peak memory 243132 kb
Host smart-bad09c7a-32f0-4796-b7ea-1b0ba0c5ce4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589380896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.3589380896 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/34.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/34.kmac_error.3887383442
Short name T1035
Test name
Test status
Simulation time 17480930413 ps
CPU time 401.54 seconds
Started May 21 12:56:25 PM PDT 24
Finished May 21 01:03:07 PM PDT 24
Peak memory 259484 kb
Host smart-3cbb4ae2-6cec-44f6-bc92-0dc1cc56011a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887383442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.3887383442 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_error/latest

Test location /workspace/coverage/default/34.kmac_key_error.345929636
Short name T554
Test name
Test status
Simulation time 1465538645 ps
CPU time 6.28 seconds
Started May 21 12:56:25 PM PDT 24
Finished May 21 12:56:32 PM PDT 24
Peak memory 218468 kb
Host smart-841af903-ae5b-483a-8403-e604a2d2097c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345929636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.345929636 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_key_error/latest

Test location /workspace/coverage/default/34.kmac_lc_escalation.3993874749
Short name T497
Test name
Test status
Simulation time 82939659 ps
CPU time 1.34 seconds
Started May 21 12:56:21 PM PDT 24
Finished May 21 12:56:23 PM PDT 24
Peak memory 218648 kb
Host smart-5292f6ba-7340-48e3-99de-dce6fcd089d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993874749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.3993874749 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/34.kmac_lc_escalation/latest

Test location /workspace/coverage/default/34.kmac_long_msg_and_output.2254456920
Short name T557
Test name
Test status
Simulation time 58604755483 ps
CPU time 1973.54 seconds
Started May 21 12:56:14 PM PDT 24
Finished May 21 01:29:09 PM PDT 24
Peak memory 394220 kb
Host smart-45449956-a79f-4d45-bd33-2a2ad34ffa0c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254456920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_a
nd_output.2254456920 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/34.kmac_sideload.3068769003
Short name T225
Test name
Test status
Simulation time 41949765832 ps
CPU time 76.84 seconds
Started May 21 12:56:13 PM PDT 24
Finished May 21 12:57:32 PM PDT 24
Peak memory 229584 kb
Host smart-e41aed29-c320-4386-a1a3-b70118939ca7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068769003 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.3068769003 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_sideload/latest

Test location /workspace/coverage/default/34.kmac_smoke.4219513946
Short name T831
Test name
Test status
Simulation time 5282973522 ps
CPU time 56.4 seconds
Started May 21 12:56:14 PM PDT 24
Finished May 21 12:57:12 PM PDT 24
Peak memory 226732 kb
Host smart-78a40307-44e8-42cf-bc2e-df40df89c752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219513946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.4219513946 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_smoke/latest

Test location /workspace/coverage/default/34.kmac_stress_all.793357062
Short name T977
Test name
Test status
Simulation time 8643895900 ps
CPU time 76.98 seconds
Started May 21 12:56:19 PM PDT 24
Finished May 21 12:57:36 PM PDT 24
Peak memory 236228 kb
Host smart-b6273e16-3e9e-4870-9d42-e5134fec2082
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=793357062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.793357062 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_stress_all/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac.1065077420
Short name T409
Test name
Test status
Simulation time 846327680 ps
CPU time 6.63 seconds
Started May 21 12:56:22 PM PDT 24
Finished May 21 12:56:29 PM PDT 24
Peak memory 219612 kb
Host smart-e0d136f3-aba7-4dee-a588-abe44e5a5a12
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065077420 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.kmac_test_vectors_kmac.1065077420 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac_xof.559870200
Short name T830
Test name
Test status
Simulation time 451339832 ps
CPU time 5.64 seconds
Started May 21 12:56:20 PM PDT 24
Finished May 21 12:56:26 PM PDT 24
Peak memory 218616 kb
Host smart-e659fa5c-fcc4-44a6-a392-aff8f433bcdb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559870200 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.kmac_test_vectors_kmac_xof.559870200 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_224.3634372125
Short name T716
Test name
Test status
Simulation time 83476360853 ps
CPU time 2315.1 seconds
Started May 21 12:56:14 PM PDT 24
Finished May 21 01:34:51 PM PDT 24
Peak memory 393108 kb
Host smart-704638cf-0592-40ee-932a-8456e172e997
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3634372125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_224.3634372125 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_256.3866730569
Short name T950
Test name
Test status
Simulation time 241843165564 ps
CPU time 2048.14 seconds
Started May 21 12:56:13 PM PDT 24
Finished May 21 01:30:23 PM PDT 24
Peak memory 379724 kb
Host smart-77147a23-7f9d-4a2c-89fd-92cb0899712c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3866730569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_256.3866730569 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_384.4114840412
Short name T814
Test name
Test status
Simulation time 14911804025 ps
CPU time 1508.05 seconds
Started May 21 12:56:15 PM PDT 24
Finished May 21 01:21:24 PM PDT 24
Peak memory 341420 kb
Host smart-e5b7aa28-15ab-422e-8b77-9e66274d268a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4114840412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_384.4114840412 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_512.77213119
Short name T344
Test name
Test status
Simulation time 71951631403 ps
CPU time 1255.45 seconds
Started May 21 12:56:18 PM PDT 24
Finished May 21 01:17:15 PM PDT 24
Peak memory 300624 kb
Host smart-b876d5fe-be1c-4a08-8251-c753b16ac00c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=77213119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_512.77213119 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_shake_128.4136698728
Short name T272
Test name
Test status
Simulation time 1034865845109 ps
CPU time 6075.21 seconds
Started May 21 12:56:19 PM PDT 24
Finished May 21 02:37:36 PM PDT 24
Peak memory 661340 kb
Host smart-14d7981d-061d-4ba2-9269-ba02a35aa39d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4136698728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_128.4136698728 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_shake_256.3739035058
Short name T381
Test name
Test status
Simulation time 896748316573 ps
CPU time 5508.49 seconds
Started May 21 12:56:21 PM PDT 24
Finished May 21 02:28:11 PM PDT 24
Peak memory 557280 kb
Host smart-3298ee69-a6d6-4a1d-bdc4-64451db0ec8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3739035058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_256.3739035058 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/35.kmac_alert_test.3039967171
Short name T757
Test name
Test status
Simulation time 18844393 ps
CPU time 0.86 seconds
Started May 21 12:56:37 PM PDT 24
Finished May 21 12:56:40 PM PDT 24
Peak memory 220584 kb
Host smart-6b2a2cb8-a462-44c8-acab-9c6f2805b940
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039967171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.3039967171 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_alert_test/latest

Test location /workspace/coverage/default/35.kmac_burst_write.1580965286
Short name T824
Test name
Test status
Simulation time 15004061148 ps
CPU time 1581.09 seconds
Started May 21 12:56:25 PM PDT 24
Finished May 21 01:22:47 PM PDT 24
Peak memory 238320 kb
Host smart-0345f12b-b09c-400e-b1ce-cb1f205c3a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580965286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.1580965286 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_burst_write/latest

Test location /workspace/coverage/default/35.kmac_entropy_refresh.2509453576
Short name T827
Test name
Test status
Simulation time 17233221621 ps
CPU time 152.75 seconds
Started May 21 12:56:32 PM PDT 24
Finished May 21 12:59:06 PM PDT 24
Peak memory 239388 kb
Host smart-1711a2b8-0d00-45fb-b6ec-441518b97717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509453576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.2509453576 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/35.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/35.kmac_error.795067836
Short name T382
Test name
Test status
Simulation time 8721330768 ps
CPU time 297.09 seconds
Started May 21 12:56:31 PM PDT 24
Finished May 21 01:01:29 PM PDT 24
Peak memory 257088 kb
Host smart-98afa699-76ab-4d3f-bfb8-0f68aaa51214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795067836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.795067836 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_error/latest

Test location /workspace/coverage/default/35.kmac_key_error.4103944952
Short name T361
Test name
Test status
Simulation time 249802105 ps
CPU time 1.26 seconds
Started May 21 12:56:32 PM PDT 24
Finished May 21 12:56:34 PM PDT 24
Peak memory 218336 kb
Host smart-73d0d919-ddc8-49ec-a5ba-6c5abb8dd7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103944952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.4103944952 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_key_error/latest

Test location /workspace/coverage/default/35.kmac_lc_escalation.1310150804
Short name T44
Test name
Test status
Simulation time 2063306766 ps
CPU time 26.32 seconds
Started May 21 12:56:31 PM PDT 24
Finished May 21 12:56:58 PM PDT 24
Peak memory 236060 kb
Host smart-10051e80-0b4b-46c6-86ff-2dc17069a153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310150804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.1310150804 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/35.kmac_lc_escalation/latest

Test location /workspace/coverage/default/35.kmac_long_msg_and_output.4016918834
Short name T930
Test name
Test status
Simulation time 111538344170 ps
CPU time 907.29 seconds
Started May 21 12:56:24 PM PDT 24
Finished May 21 01:11:32 PM PDT 24
Peak memory 299144 kb
Host smart-cc6e868d-e851-4e0b-b4b3-2203406ed666
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016918834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_a
nd_output.4016918834 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/35.kmac_sideload.2691181591
Short name T585
Test name
Test status
Simulation time 2354413178 ps
CPU time 80.66 seconds
Started May 21 12:56:26 PM PDT 24
Finished May 21 12:57:48 PM PDT 24
Peak memory 236532 kb
Host smart-45480038-82dd-4a0d-8e3e-7c79a6243c88
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691181591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.2691181591 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_sideload/latest

Test location /workspace/coverage/default/35.kmac_smoke.3632981146
Short name T963
Test name
Test status
Simulation time 5724753548 ps
CPU time 37.53 seconds
Started May 21 12:56:25 PM PDT 24
Finished May 21 12:57:03 PM PDT 24
Peak memory 226768 kb
Host smart-67b89132-a4e8-439d-a741-f77f9bd864f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632981146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.3632981146 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_smoke/latest

Test location /workspace/coverage/default/35.kmac_stress_all.3733647277
Short name T638
Test name
Test status
Simulation time 186807940443 ps
CPU time 1762.53 seconds
Started May 21 12:56:32 PM PDT 24
Finished May 21 01:25:56 PM PDT 24
Peak memory 369000 kb
Host smart-9fce37c7-1e90-4039-bd82-254ce718cbff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3733647277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.3733647277 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_stress_all/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac.1604139048
Short name T509
Test name
Test status
Simulation time 383161668 ps
CPU time 6.34 seconds
Started May 21 12:56:24 PM PDT 24
Finished May 21 12:56:31 PM PDT 24
Peak memory 218524 kb
Host smart-70c606c7-de81-4e10-b2fc-60ffead81342
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604139048 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.kmac_test_vectors_kmac.1604139048 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac_xof.4049808114
Short name T609
Test name
Test status
Simulation time 111583421 ps
CPU time 5.29 seconds
Started May 21 12:56:25 PM PDT 24
Finished May 21 12:56:31 PM PDT 24
Peak memory 226628 kb
Host smart-b044c17b-94f3-40eb-a4e2-2d628d2aaa76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049808114 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.kmac_test_vectors_kmac_xof.4049808114 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_224.2915298043
Short name T39
Test name
Test status
Simulation time 22201616857 ps
CPU time 1852.65 seconds
Started May 21 12:56:28 PM PDT 24
Finished May 21 01:27:21 PM PDT 24
Peak memory 395072 kb
Host smart-8776bc66-0394-4da5-8817-22d8091c81f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2915298043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_224.2915298043 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_256.443108249
Short name T373
Test name
Test status
Simulation time 262274734756 ps
CPU time 2206.8 seconds
Started May 21 12:56:25 PM PDT 24
Finished May 21 01:33:13 PM PDT 24
Peak memory 393004 kb
Host smart-91f5909b-8f63-47fd-98dc-e005036d6bed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=443108249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_256.443108249 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_384.2243231142
Short name T476
Test name
Test status
Simulation time 39461407835 ps
CPU time 1498.59 seconds
Started May 21 12:56:25 PM PDT 24
Finished May 21 01:21:25 PM PDT 24
Peak memory 343036 kb
Host smart-6c0ec869-3c48-4a45-8a14-b9e9a124cf9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2243231142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_384.2243231142 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_512.3783315369
Short name T544
Test name
Test status
Simulation time 102635272418 ps
CPU time 1299.38 seconds
Started May 21 12:56:26 PM PDT 24
Finished May 21 01:18:07 PM PDT 24
Peak memory 300512 kb
Host smart-ce517f12-d9f5-4eec-9eba-58d8175302a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3783315369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_512.3783315369 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_shake_128.677972824
Short name T375
Test name
Test status
Simulation time 60652019264 ps
CPU time 4842.32 seconds
Started May 21 12:56:26 PM PDT 24
Finished May 21 02:17:10 PM PDT 24
Peak memory 654740 kb
Host smart-4186e556-c26c-4335-b4bb-5f95e0a3998c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=677972824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_128.677972824 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_shake_256.3772477176
Short name T940
Test name
Test status
Simulation time 229350969315 ps
CPU time 5257.9 seconds
Started May 21 12:56:25 PM PDT 24
Finished May 21 02:24:03 PM PDT 24
Peak memory 575504 kb
Host smart-26d765fc-fa8c-4956-a144-119d79f436cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3772477176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_256.3772477176 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/36.kmac_alert_test.712773852
Short name T648
Test name
Test status
Simulation time 43548282 ps
CPU time 0.8 seconds
Started May 21 12:56:57 PM PDT 24
Finished May 21 12:56:59 PM PDT 24
Peak memory 218508 kb
Host smart-22124aa1-10f6-4f33-88cf-bd59b05308a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712773852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.712773852 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/36.kmac_alert_test/latest

Test location /workspace/coverage/default/36.kmac_app.2428567824
Short name T480
Test name
Test status
Simulation time 6201832373 ps
CPU time 92.55 seconds
Started May 21 12:56:50 PM PDT 24
Finished May 21 12:58:23 PM PDT 24
Peak memory 231832 kb
Host smart-c1d1e17c-fdd6-4af3-83aa-2966a92d3eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428567824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.2428567824 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_app/latest

Test location /workspace/coverage/default/36.kmac_burst_write.762496140
Short name T809
Test name
Test status
Simulation time 13137534002 ps
CPU time 660.87 seconds
Started May 21 12:56:37 PM PDT 24
Finished May 21 01:07:40 PM PDT 24
Peak memory 234612 kb
Host smart-0218ecf8-56a2-4198-9d6d-424834b96d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762496140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.762496140 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_burst_write/latest

Test location /workspace/coverage/default/36.kmac_entropy_refresh.2946854883
Short name T848
Test name
Test status
Simulation time 37634097028 ps
CPU time 118.9 seconds
Started May 21 12:56:48 PM PDT 24
Finished May 21 12:58:47 PM PDT 24
Peak memory 234532 kb
Host smart-54045ab2-ebcf-4612-b544-51990a7ab316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946854883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.2946854883 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/36.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/36.kmac_error.1507103971
Short name T371
Test name
Test status
Simulation time 27743641196 ps
CPU time 352.62 seconds
Started May 21 12:56:49 PM PDT 24
Finished May 21 01:02:42 PM PDT 24
Peak memory 257944 kb
Host smart-d207095d-2e15-493f-858b-f23eaf22c4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507103971 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.1507103971 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_error/latest

Test location /workspace/coverage/default/36.kmac_key_error.1708477171
Short name T269
Test name
Test status
Simulation time 1606518422 ps
CPU time 13.01 seconds
Started May 21 12:56:49 PM PDT 24
Finished May 21 12:57:02 PM PDT 24
Peak memory 218556 kb
Host smart-6e3d3b6e-97e9-4c9a-bdc7-6211ed65d275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708477171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.1708477171 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_key_error/latest

Test location /workspace/coverage/default/36.kmac_lc_escalation.1600758656
Short name T56
Test name
Test status
Simulation time 60999365 ps
CPU time 1.48 seconds
Started May 21 12:56:49 PM PDT 24
Finished May 21 12:56:52 PM PDT 24
Peak memory 218684 kb
Host smart-533bbdcb-7cab-4e18-81d5-b18cb0312c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600758656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.1600758656 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/36.kmac_lc_escalation/latest

Test location /workspace/coverage/default/36.kmac_long_msg_and_output.2110437850
Short name T185
Test name
Test status
Simulation time 71491926752 ps
CPU time 2664.72 seconds
Started May 21 12:56:37 PM PDT 24
Finished May 21 01:41:04 PM PDT 24
Peak memory 431740 kb
Host smart-d8207568-7f2b-442e-a7ed-8ae1c197cc75
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110437850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_a
nd_output.2110437850 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/36.kmac_sideload.790653450
Short name T556
Test name
Test status
Simulation time 79602676568 ps
CPU time 453.64 seconds
Started May 21 12:56:37 PM PDT 24
Finished May 21 01:04:12 PM PDT 24
Peak memory 255928 kb
Host smart-bcfc2602-0c41-41ae-ad65-a038b04b34a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790653450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.790653450 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_sideload/latest

Test location /workspace/coverage/default/36.kmac_smoke.1150022049
Short name T540
Test name
Test status
Simulation time 3938093900 ps
CPU time 39.07 seconds
Started May 21 12:56:41 PM PDT 24
Finished May 21 12:57:21 PM PDT 24
Peak memory 219572 kb
Host smart-0cfb568e-9616-4922-8f6b-4dc1bd921a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150022049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.1150022049 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_smoke/latest

Test location /workspace/coverage/default/36.kmac_stress_all.1599380986
Short name T817
Test name
Test status
Simulation time 14820657551 ps
CPU time 1134.29 seconds
Started May 21 12:56:54 PM PDT 24
Finished May 21 01:15:49 PM PDT 24
Peak memory 374144 kb
Host smart-9437e037-7745-4c6e-87bb-43e04ef263e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1599380986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.1599380986 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_stress_all/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac.3300564963
Short name T921
Test name
Test status
Simulation time 691692698 ps
CPU time 5.35 seconds
Started May 21 12:56:43 PM PDT 24
Finished May 21 12:56:49 PM PDT 24
Peak memory 218452 kb
Host smart-6d7976da-00c5-4887-8b0f-915b32e6b1e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300564963 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.kmac_test_vectors_kmac.3300564963 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac_xof.3233228200
Short name T608
Test name
Test status
Simulation time 465578743 ps
CPU time 5.75 seconds
Started May 21 12:56:50 PM PDT 24
Finished May 21 12:56:56 PM PDT 24
Peak memory 219756 kb
Host smart-2ba46ee4-b5bb-4e20-8166-8515222a43fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233228200 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.kmac_test_vectors_kmac_xof.3233228200 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_224.3686679669
Short name T258
Test name
Test status
Simulation time 382924283922 ps
CPU time 2413.18 seconds
Started May 21 12:56:36 PM PDT 24
Finished May 21 01:36:50 PM PDT 24
Peak memory 394292 kb
Host smart-4616240a-be4e-474e-b952-f2673fc148c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3686679669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_224.3686679669 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_256.3728665790
Short name T517
Test name
Test status
Simulation time 19775716588 ps
CPU time 1846.2 seconds
Started May 21 12:56:36 PM PDT 24
Finished May 21 01:27:23 PM PDT 24
Peak memory 384904 kb
Host smart-7d730770-7070-490a-9b24-50d7e577c46a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3728665790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_256.3728665790 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_384.4040816286
Short name T464
Test name
Test status
Simulation time 276606166607 ps
CPU time 1826.14 seconds
Started May 21 12:56:36 PM PDT 24
Finished May 21 01:27:05 PM PDT 24
Peak memory 337004 kb
Host smart-17cbb393-a356-4bdd-9f3a-8dcf78ae3cf4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4040816286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_384.4040816286 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_512.3852894931
Short name T818
Test name
Test status
Simulation time 48077618387 ps
CPU time 1302.48 seconds
Started May 21 12:56:41 PM PDT 24
Finished May 21 01:18:25 PM PDT 24
Peak memory 296020 kb
Host smart-07b51993-ca36-40cd-9cb7-cd02204acbe7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3852894931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_512.3852894931 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_shake_128.806469947
Short name T16
Test name
Test status
Simulation time 260748337062 ps
CPU time 5436.92 seconds
Started May 21 12:56:43 PM PDT 24
Finished May 21 02:27:22 PM PDT 24
Peak memory 659896 kb
Host smart-cb04e5e3-1344-413d-98dc-65c2fa512f0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=806469947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_128.806469947 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/37.kmac_alert_test.2339439410
Short name T537
Test name
Test status
Simulation time 18194676 ps
CPU time 0.9 seconds
Started May 21 12:57:09 PM PDT 24
Finished May 21 12:57:10 PM PDT 24
Peak memory 218760 kb
Host smart-e3fa612e-f129-4952-87d4-9036dd9df7d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339439410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.2339439410 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_alert_test/latest

Test location /workspace/coverage/default/37.kmac_app.878171369
Short name T944
Test name
Test status
Simulation time 42019731161 ps
CPU time 308.65 seconds
Started May 21 12:57:01 PM PDT 24
Finished May 21 01:02:10 PM PDT 24
Peak memory 249612 kb
Host smart-0b490d52-43c3-4ddc-8093-3696f394cdf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878171369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.878171369 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_app/latest

Test location /workspace/coverage/default/37.kmac_burst_write.4096661484
Short name T388
Test name
Test status
Simulation time 11774957615 ps
CPU time 949.75 seconds
Started May 21 12:56:54 PM PDT 24
Finished May 21 01:12:45 PM PDT 24
Peak memory 235412 kb
Host smart-7bd37ab3-1926-424e-8af2-e6335df09e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096661484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.4096661484 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_burst_write/latest

Test location /workspace/coverage/default/37.kmac_entropy_refresh.297105780
Short name T380
Test name
Test status
Simulation time 4664656160 ps
CPU time 220.75 seconds
Started May 21 12:57:01 PM PDT 24
Finished May 21 01:00:42 PM PDT 24
Peak memory 245788 kb
Host smart-14b2775b-3cf9-4886-af77-d3bed23ca369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297105780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.297105780 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/37.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/37.kmac_error.1664486938
Short name T679
Test name
Test status
Simulation time 15435753309 ps
CPU time 384.61 seconds
Started May 21 12:57:06 PM PDT 24
Finished May 21 01:03:32 PM PDT 24
Peak memory 267648 kb
Host smart-496cdd16-804e-48b3-8305-1ee5231ff745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664486938 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.1664486938 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_error/latest

Test location /workspace/coverage/default/37.kmac_key_error.3396035367
Short name T806
Test name
Test status
Simulation time 22286801580 ps
CPU time 8.51 seconds
Started May 21 12:57:05 PM PDT 24
Finished May 21 12:57:14 PM PDT 24
Peak memory 218604 kb
Host smart-914b6496-e692-4bd8-96d0-8b1204ca0756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396035367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.3396035367 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_key_error/latest

Test location /workspace/coverage/default/37.kmac_lc_escalation.1958101629
Short name T26
Test name
Test status
Simulation time 138049948 ps
CPU time 1.29 seconds
Started May 21 12:57:06 PM PDT 24
Finished May 21 12:57:08 PM PDT 24
Peak memory 218612 kb
Host smart-f564ca21-b3d0-4c1a-b33b-4d970f210fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958101629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.1958101629 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/37.kmac_lc_escalation/latest

Test location /workspace/coverage/default/37.kmac_long_msg_and_output.2233943090
Short name T1
Test name
Test status
Simulation time 394009696849 ps
CPU time 2871.43 seconds
Started May 21 12:56:55 PM PDT 24
Finished May 21 01:44:48 PM PDT 24
Peak memory 444096 kb
Host smart-5811c919-b504-472d-abf8-2cf8e8a082c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233943090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_a
nd_output.2233943090 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/37.kmac_sideload.1339015357
Short name T850
Test name
Test status
Simulation time 5840987153 ps
CPU time 212.99 seconds
Started May 21 12:56:53 PM PDT 24
Finished May 21 01:00:27 PM PDT 24
Peak memory 239076 kb
Host smart-4f422edc-f943-4c6a-a3c6-3f1eae8dc3d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339015357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.1339015357 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_sideload/latest

Test location /workspace/coverage/default/37.kmac_smoke.3125724404
Short name T691
Test name
Test status
Simulation time 3635328605 ps
CPU time 21.32 seconds
Started May 21 12:56:55 PM PDT 24
Finished May 21 12:57:17 PM PDT 24
Peak memory 220696 kb
Host smart-2d12849f-cdb3-4623-bf2b-1a53a8b37868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125724404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.3125724404 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_smoke/latest

Test location /workspace/coverage/default/37.kmac_stress_all.1452065467
Short name T334
Test name
Test status
Simulation time 10633692744 ps
CPU time 189.3 seconds
Started May 21 12:57:06 PM PDT 24
Finished May 21 01:00:17 PM PDT 24
Peak memory 251600 kb
Host smart-e9089fce-b1be-465d-9d1f-25b0b75abb28
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1452065467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.1452065467 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_stress_all/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac.1145980854
Short name T666
Test name
Test status
Simulation time 1113583842 ps
CPU time 5.97 seconds
Started May 21 12:57:02 PM PDT 24
Finished May 21 12:57:08 PM PDT 24
Peak memory 226700 kb
Host smart-626fb2bd-aae3-4e5a-8eeb-bb867e45387d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145980854 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.kmac_test_vectors_kmac.1145980854 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac_xof.1076909062
Short name T653
Test name
Test status
Simulation time 1100459433 ps
CPU time 6.18 seconds
Started May 21 12:57:01 PM PDT 24
Finished May 21 12:57:08 PM PDT 24
Peak memory 226704 kb
Host smart-6ad06af4-8a40-42f5-844e-0dd2177a8f1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076909062 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.kmac_test_vectors_kmac_xof.1076909062 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_224.2675786054
Short name T495
Test name
Test status
Simulation time 280665531296 ps
CPU time 2133.49 seconds
Started May 21 12:57:00 PM PDT 24
Finished May 21 01:32:34 PM PDT 24
Peak memory 391892 kb
Host smart-66a02f42-3344-4800-a736-1885a5477f8f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2675786054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_224.2675786054 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_256.3608448208
Short name T829
Test name
Test status
Simulation time 20683428936 ps
CPU time 1966.79 seconds
Started May 21 12:57:00 PM PDT 24
Finished May 21 01:29:48 PM PDT 24
Peak memory 384476 kb
Host smart-17ff9881-24a0-4979-8f26-8debcc9a9dca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3608448208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_256.3608448208 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_384.2333427488
Short name T1051
Test name
Test status
Simulation time 534105678615 ps
CPU time 1806.55 seconds
Started May 21 12:56:59 PM PDT 24
Finished May 21 01:27:07 PM PDT 24
Peak memory 335172 kb
Host smart-80a41ea4-483b-4361-8a38-18ed8952edd3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2333427488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_384.2333427488 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_512.1013207883
Short name T980
Test name
Test status
Simulation time 44560223882 ps
CPU time 1353.64 seconds
Started May 21 12:57:01 PM PDT 24
Finished May 21 01:19:35 PM PDT 24
Peak memory 300576 kb
Host smart-e8ce74c7-812c-4763-8b67-1380354b60fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1013207883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_512.1013207883 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_128.4280325295
Short name T355
Test name
Test status
Simulation time 931600282376 ps
CPU time 5332.74 seconds
Started May 21 12:57:00 PM PDT 24
Finished May 21 02:25:54 PM PDT 24
Peak memory 649252 kb
Host smart-6d54914d-18d5-40e4-a49e-9e2c566e9b62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4280325295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_128.4280325295 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_256.595650100
Short name T784
Test name
Test status
Simulation time 347501486116 ps
CPU time 4272.75 seconds
Started May 21 12:57:02 PM PDT 24
Finished May 21 02:08:15 PM PDT 24
Peak memory 565152 kb
Host smart-a9c69667-73ea-455c-abd4-0e2130915fc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=595650100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_256.595650100 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/38.kmac_alert_test.2596431583
Short name T974
Test name
Test status
Simulation time 15659867 ps
CPU time 0.92 seconds
Started May 21 12:57:23 PM PDT 24
Finished May 21 12:57:24 PM PDT 24
Peak memory 220588 kb
Host smart-fd490117-f2fd-4f86-857a-c166fa53aaba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596431583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.2596431583 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_alert_test/latest

Test location /workspace/coverage/default/38.kmac_app.2050854464
Short name T155
Test name
Test status
Simulation time 2577760642 ps
CPU time 143.96 seconds
Started May 21 12:57:20 PM PDT 24
Finished May 21 12:59:44 PM PDT 24
Peak memory 236448 kb
Host smart-9941c2af-882a-47a1-83a9-a10c80571315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050854464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.2050854464 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_app/latest

Test location /workspace/coverage/default/38.kmac_burst_write.3344163576
Short name T93
Test name
Test status
Simulation time 5767783941 ps
CPU time 147.14 seconds
Started May 21 12:57:07 PM PDT 24
Finished May 21 12:59:35 PM PDT 24
Peak memory 226696 kb
Host smart-f964ce13-54ac-4d92-a5de-2673b63f354e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344163576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.3344163576 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_burst_write/latest

Test location /workspace/coverage/default/38.kmac_entropy_refresh.3589001598
Short name T137
Test name
Test status
Simulation time 44775112603 ps
CPU time 102.52 seconds
Started May 21 12:57:22 PM PDT 24
Finished May 21 12:59:05 PM PDT 24
Peak memory 233964 kb
Host smart-c7472e92-f581-4f0b-bfb2-3382a5d93489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589001598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.3589001598 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/38.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/38.kmac_error.490363830
Short name T455
Test name
Test status
Simulation time 24667562547 ps
CPU time 353.55 seconds
Started May 21 12:57:20 PM PDT 24
Finished May 21 01:03:14 PM PDT 24
Peak memory 270328 kb
Host smart-b7223ac2-eb68-4160-a619-9734fd99d7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490363830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.490363830 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_error/latest

Test location /workspace/coverage/default/38.kmac_key_error.3891231902
Short name T390
Test name
Test status
Simulation time 803918783 ps
CPU time 6.74 seconds
Started May 21 12:57:20 PM PDT 24
Finished May 21 12:57:28 PM PDT 24
Peak memory 222884 kb
Host smart-453f92f6-ac6c-4744-bccd-294656427d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891231902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.3891231902 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_key_error/latest

Test location /workspace/coverage/default/38.kmac_lc_escalation.2211220048
Short name T78
Test name
Test status
Simulation time 42253823 ps
CPU time 1.33 seconds
Started May 21 12:57:20 PM PDT 24
Finished May 21 12:57:22 PM PDT 24
Peak memory 218628 kb
Host smart-9b301d11-778b-4d4c-99a8-c33f37002656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211220048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.2211220048 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/38.kmac_lc_escalation/latest

Test location /workspace/coverage/default/38.kmac_long_msg_and_output.557799558
Short name T192
Test name
Test status
Simulation time 493803033141 ps
CPU time 2311.07 seconds
Started May 21 12:57:06 PM PDT 24
Finished May 21 01:35:38 PM PDT 24
Peak memory 406656 kb
Host smart-04d50d7e-6bcb-4790-9db5-befbfa3e1d17
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557799558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_an
d_output.557799558 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/38.kmac_sideload.648109181
Short name T304
Test name
Test status
Simulation time 76464935738 ps
CPU time 464.92 seconds
Started May 21 12:57:07 PM PDT 24
Finished May 21 01:04:52 PM PDT 24
Peak memory 250880 kb
Host smart-dc39087d-85c3-4359-a03d-2c5b9640ce76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648109181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.648109181 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_sideload/latest

Test location /workspace/coverage/default/38.kmac_smoke.1507997943
Short name T559
Test name
Test status
Simulation time 918608059 ps
CPU time 17.47 seconds
Started May 21 12:57:05 PM PDT 24
Finished May 21 12:57:23 PM PDT 24
Peak memory 226748 kb
Host smart-5e9f294d-f7a9-438a-af52-94c95d1ed9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507997943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.1507997943 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_smoke/latest

Test location /workspace/coverage/default/38.kmac_stress_all.799202530
Short name T285
Test name
Test status
Simulation time 40547100753 ps
CPU time 1646.5 seconds
Started May 21 12:57:19 PM PDT 24
Finished May 21 01:24:46 PM PDT 24
Peak memory 307080 kb
Host smart-e00a7281-4f34-4386-a6d0-ded6a960fd9d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=799202530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.799202530 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_stress_all/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac.197713554
Short name T106
Test name
Test status
Simulation time 224063224 ps
CPU time 5.81 seconds
Started May 21 12:57:11 PM PDT 24
Finished May 21 12:57:17 PM PDT 24
Peak memory 218612 kb
Host smart-033b1b7a-4d87-4970-9ac5-10aba10083a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197713554 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.kmac_test_vectors_kmac.197713554 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac_xof.2314377508
Short name T290
Test name
Test status
Simulation time 179476414 ps
CPU time 6.83 seconds
Started May 21 12:57:20 PM PDT 24
Finished May 21 12:57:27 PM PDT 24
Peak memory 218628 kb
Host smart-4786b4cf-3f52-42e6-89c4-781453acc12f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314377508 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.kmac_test_vectors_kmac_xof.2314377508 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_224.225430680
Short name T173
Test name
Test status
Simulation time 83366712399 ps
CPU time 2307.96 seconds
Started May 21 12:57:05 PM PDT 24
Finished May 21 01:35:34 PM PDT 24
Peak memory 389112 kb
Host smart-a66b5c28-d259-459c-9e1b-431f53da966f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=225430680 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_224.225430680 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_256.3399776231
Short name T305
Test name
Test status
Simulation time 63645665431 ps
CPU time 2106.53 seconds
Started May 21 12:57:07 PM PDT 24
Finished May 21 01:32:14 PM PDT 24
Peak memory 393484 kb
Host smart-a8a44b19-5ba5-4d71-8427-98b181f6f28b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3399776231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_256.3399776231 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_384.2983210200
Short name T366
Test name
Test status
Simulation time 15557518435 ps
CPU time 1575.71 seconds
Started May 21 12:57:05 PM PDT 24
Finished May 21 01:23:22 PM PDT 24
Peak memory 342404 kb
Host smart-17aefd4c-8080-4f15-a4e4-7702fe389443
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2983210200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_384.2983210200 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_512.3763557432
Short name T191
Test name
Test status
Simulation time 172926166153 ps
CPU time 1282.6 seconds
Started May 21 12:57:11 PM PDT 24
Finished May 21 01:18:34 PM PDT 24
Peak memory 303356 kb
Host smart-8e8765c1-468e-4fa6-ab70-2824720b8f14
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3763557432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_512.3763557432 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_128.4049981778
Short name T884
Test name
Test status
Simulation time 1201367922227 ps
CPU time 5124.25 seconds
Started May 21 12:57:10 PM PDT 24
Finished May 21 02:22:36 PM PDT 24
Peak memory 653704 kb
Host smart-87723ce2-1fab-435c-a95e-b623553d0a69
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4049981778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_128.4049981778 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_256.1202280
Short name T451
Test name
Test status
Simulation time 194921017723 ps
CPU time 4782.3 seconds
Started May 21 12:57:12 PM PDT 24
Finished May 21 02:16:55 PM PDT 24
Peak memory 569240 kb
Host smart-f8806857-1c54-44b8-8d0f-54659af889d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1202280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_256.1202280 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/39.kmac_alert_test.3674794661
Short name T535
Test name
Test status
Simulation time 44683116 ps
CPU time 0.81 seconds
Started May 21 12:57:38 PM PDT 24
Finished May 21 12:57:39 PM PDT 24
Peak memory 220560 kb
Host smart-78ce63b7-339a-4a4f-b2e5-e80ed5ee2b85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674794661 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.3674794661 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_alert_test/latest

Test location /workspace/coverage/default/39.kmac_app.572399409
Short name T564
Test name
Test status
Simulation time 3661450838 ps
CPU time 163.7 seconds
Started May 21 12:57:31 PM PDT 24
Finished May 21 01:00:16 PM PDT 24
Peak memory 240036 kb
Host smart-3e39c5a2-f1d3-4498-8100-84a9b8e4493b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572399409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.572399409 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_app/latest

Test location /workspace/coverage/default/39.kmac_burst_write.4116411912
Short name T756
Test name
Test status
Simulation time 14810431497 ps
CPU time 458.53 seconds
Started May 21 12:57:27 PM PDT 24
Finished May 21 01:05:06 PM PDT 24
Peak memory 233220 kb
Host smart-b1926bbb-e20b-4adb-ab19-1163c4e4828e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116411912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.4116411912 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_burst_write/latest

Test location /workspace/coverage/default/39.kmac_entropy_refresh.1290777146
Short name T749
Test name
Test status
Simulation time 924938304 ps
CPU time 19.68 seconds
Started May 21 12:57:32 PM PDT 24
Finished May 21 12:57:53 PM PDT 24
Peak memory 226732 kb
Host smart-4c2993b8-823f-4e66-8ed7-0ad53993ec0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290777146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.1290777146 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/39.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/39.kmac_error.2676700850
Short name T1056
Test name
Test status
Simulation time 11650761509 ps
CPU time 347 seconds
Started May 21 12:57:32 PM PDT 24
Finished May 21 01:03:20 PM PDT 24
Peak memory 259520 kb
Host smart-3e043565-5add-40db-8108-35f4abe99491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676700850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.2676700850 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_error/latest

Test location /workspace/coverage/default/39.kmac_key_error.475387076
Short name T607
Test name
Test status
Simulation time 316678962 ps
CPU time 2.62 seconds
Started May 21 12:57:40 PM PDT 24
Finished May 21 12:57:43 PM PDT 24
Peak memory 218496 kb
Host smart-c8b23d6b-2890-4dab-8beb-338fe705eebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475387076 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.475387076 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_key_error/latest

Test location /workspace/coverage/default/39.kmac_lc_escalation.566337163
Short name T997
Test name
Test status
Simulation time 60934198 ps
CPU time 1.29 seconds
Started May 21 12:57:39 PM PDT 24
Finished May 21 12:57:40 PM PDT 24
Peak memory 218700 kb
Host smart-8a6895e1-bff3-460b-8515-8dd5256fd65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566337163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.566337163 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/39.kmac_lc_escalation/latest

Test location /workspace/coverage/default/39.kmac_long_msg_and_output.1092199824
Short name T181
Test name
Test status
Simulation time 228324720573 ps
CPU time 3071.12 seconds
Started May 21 12:57:26 PM PDT 24
Finished May 21 01:48:38 PM PDT 24
Peak memory 474980 kb
Host smart-63a3d371-e26a-405a-bf0a-3615bba2e755
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092199824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_a
nd_output.1092199824 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/39.kmac_sideload.4011542235
Short name T459
Test name
Test status
Simulation time 18805652466 ps
CPU time 452.28 seconds
Started May 21 12:57:26 PM PDT 24
Finished May 21 01:04:59 PM PDT 24
Peak memory 253644 kb
Host smart-23003a6a-a220-41d2-b23b-7bd41c5b5e5c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011542235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.4011542235 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_sideload/latest

Test location /workspace/coverage/default/39.kmac_smoke.2960033391
Short name T324
Test name
Test status
Simulation time 6272522578 ps
CPU time 87.6 seconds
Started May 21 12:57:25 PM PDT 24
Finished May 21 12:58:54 PM PDT 24
Peak memory 226716 kb
Host smart-88703673-6f25-43a3-b795-1a1c383d82dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960033391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.2960033391 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_smoke/latest

Test location /workspace/coverage/default/39.kmac_stress_all.3217562332
Short name T18
Test name
Test status
Simulation time 127064747695 ps
CPU time 3323.91 seconds
Started May 21 12:57:39 PM PDT 24
Finished May 21 01:53:03 PM PDT 24
Peak memory 474876 kb
Host smart-bd94d58f-70fe-4026-8f28-86c8ed37019f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3217562332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.3217562332 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_stress_all/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac.687671046
Short name T176
Test name
Test status
Simulation time 451651431 ps
CPU time 4.88 seconds
Started May 21 12:57:31 PM PDT 24
Finished May 21 12:57:38 PM PDT 24
Peak memory 219556 kb
Host smart-1ed574e5-f0b6-488c-b4ff-b2891ce85b04
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687671046 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.kmac_test_vectors_kmac.687671046 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac_xof.3928441613
Short name T804
Test name
Test status
Simulation time 473545619 ps
CPU time 6.85 seconds
Started May 21 12:57:32 PM PDT 24
Finished May 21 12:57:40 PM PDT 24
Peak memory 218560 kb
Host smart-20f6c613-42e5-414d-af1f-24aa542e0db0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928441613 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.kmac_test_vectors_kmac_xof.3928441613 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_224.1687746449
Short name T845
Test name
Test status
Simulation time 82892015445 ps
CPU time 1796.32 seconds
Started May 21 12:57:27 PM PDT 24
Finished May 21 01:27:24 PM PDT 24
Peak memory 405960 kb
Host smart-ec7025c8-55da-4298-903f-35653ffebe10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1687746449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_224.1687746449 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_256.223140357
Short name T907
Test name
Test status
Simulation time 83961262741 ps
CPU time 2374.09 seconds
Started May 21 12:57:26 PM PDT 24
Finished May 21 01:37:02 PM PDT 24
Peak memory 387232 kb
Host smart-9ccec74b-b8ab-42e6-ae9c-6d24f1e099e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=223140357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_256.223140357 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_384.4099849595
Short name T533
Test name
Test status
Simulation time 195244759974 ps
CPU time 1586.04 seconds
Started May 21 12:57:23 PM PDT 24
Finished May 21 01:23:50 PM PDT 24
Peak memory 336700 kb
Host smart-1fe5cb6e-b740-48de-a3e1-cbb89f7a9f5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4099849595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_384.4099849595 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_512.532883561
Short name T650
Test name
Test status
Simulation time 84946431016 ps
CPU time 1234.62 seconds
Started May 21 12:57:32 PM PDT 24
Finished May 21 01:18:08 PM PDT 24
Peak memory 295972 kb
Host smart-025017f8-b605-471e-8e5a-10de3fc4d77c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=532883561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_512.532883561 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_shake_128.1674177929
Short name T142
Test name
Test status
Simulation time 947127275486 ps
CPU time 5815.7 seconds
Started May 21 12:57:32 PM PDT 24
Finished May 21 02:34:30 PM PDT 24
Peak memory 659580 kb
Host smart-977a979f-6bbf-42e9-9550-0f08d8ef2e43
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1674177929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_128.1674177929 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_shake_256.1573025402
Short name T62
Test name
Test status
Simulation time 66006775932 ps
CPU time 4371.03 seconds
Started May 21 12:57:32 PM PDT 24
Finished May 21 02:10:25 PM PDT 24
Peak memory 587000 kb
Host smart-03978422-547b-4d30-896f-58384a01cb81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1573025402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_256.1573025402 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/4.kmac_alert_test.3259499986
Short name T1010
Test name
Test status
Simulation time 24716337 ps
CPU time 0.91 seconds
Started May 21 12:53:51 PM PDT 24
Finished May 21 12:53:56 PM PDT 24
Peak memory 218528 kb
Host smart-cc6b26a4-a0a2-41ee-b31d-a3911dc29308
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259499986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.3259499986 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_alert_test/latest

Test location /workspace/coverage/default/4.kmac_app.356493364
Short name T312
Test name
Test status
Simulation time 2782715311 ps
CPU time 28.72 seconds
Started May 21 12:53:52 PM PDT 24
Finished May 21 12:54:25 PM PDT 24
Peak memory 226704 kb
Host smart-7335ab74-4061-4bce-aa02-df4c8f6476dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356493364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.356493364 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_app/latest

Test location /workspace/coverage/default/4.kmac_app_with_partial_data.2865671969
Short name T549
Test name
Test status
Simulation time 7169850510 ps
CPU time 387.2 seconds
Started May 21 12:53:27 PM PDT 24
Finished May 21 12:59:58 PM PDT 24
Peak memory 250044 kb
Host smart-2c42d881-71fb-4e9c-a382-89b2616004bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865671969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.2865671969 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/4.kmac_burst_write.1923055401
Short name T851
Test name
Test status
Simulation time 123808311846 ps
CPU time 758.38 seconds
Started May 21 12:53:30 PM PDT 24
Finished May 21 01:06:12 PM PDT 24
Peak memory 243156 kb
Host smart-a49d9fce-7eca-498b-b75b-49436dcd5c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923055401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.1923055401 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_burst_write/latest

Test location /workspace/coverage/default/4.kmac_edn_timeout_error.2160604633
Short name T500
Test name
Test status
Simulation time 501352860 ps
CPU time 40.37 seconds
Started May 21 12:53:56 PM PDT 24
Finished May 21 12:54:40 PM PDT 24
Peak memory 227896 kb
Host smart-90537c09-a6bc-4845-a828-706b56823b42
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2160604633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.2160604633 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_mode_error.2581849003
Short name T418
Test name
Test status
Simulation time 43117740 ps
CPU time 0.83 seconds
Started May 21 12:53:29 PM PDT 24
Finished May 21 12:53:33 PM PDT 24
Peak memory 220560 kb
Host smart-b421ddd2-24d1-4be0-94a5-adc51569b3bf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2581849003 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.2581849003 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_ready_error.1559176564
Short name T407
Test name
Test status
Simulation time 6589976406 ps
CPU time 65.8 seconds
Started May 21 12:53:47 PM PDT 24
Finished May 21 12:54:56 PM PDT 24
Peak memory 226788 kb
Host smart-a44f07a4-7763-4167-a567-9f7a8f99adbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559176564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.1559176564 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_refresh.3149743664
Short name T253
Test name
Test status
Simulation time 8163186798 ps
CPU time 172.81 seconds
Started May 21 12:53:42 PM PDT 24
Finished May 21 12:56:37 PM PDT 24
Peak memory 240060 kb
Host smart-574356aa-c411-4217-88cd-ffe0565c436f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149743664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.3149743664 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/4.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/4.kmac_error.1666024155
Short name T595
Test name
Test status
Simulation time 1459597598 ps
CPU time 32.37 seconds
Started May 21 12:53:58 PM PDT 24
Finished May 21 12:54:33 PM PDT 24
Peak memory 234908 kb
Host smart-e24fbc86-ad1c-4b37-a151-5090a856f9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666024155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.1666024155 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_error/latest

Test location /workspace/coverage/default/4.kmac_key_error.3840928929
Short name T683
Test name
Test status
Simulation time 6027020029 ps
CPU time 11 seconds
Started May 21 12:53:41 PM PDT 24
Finished May 21 12:53:54 PM PDT 24
Peak memory 218792 kb
Host smart-a3dbaa60-17bb-4103-8238-b751c10b0643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840928929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.3840928929 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_key_error/latest

Test location /workspace/coverage/default/4.kmac_lc_escalation.969805600
Short name T478
Test name
Test status
Simulation time 83011924 ps
CPU time 1.39 seconds
Started May 21 12:53:43 PM PDT 24
Finished May 21 12:53:47 PM PDT 24
Peak memory 218632 kb
Host smart-3809f73e-b4e6-4e4f-8055-921c44e7e983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969805600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.969805600 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_lc_escalation/latest

Test location /workspace/coverage/default/4.kmac_long_msg_and_output.1480205646
Short name T868
Test name
Test status
Simulation time 55396847507 ps
CPU time 1459.06 seconds
Started May 21 12:53:30 PM PDT 24
Finished May 21 01:17:53 PM PDT 24
Peak memory 354892 kb
Host smart-e4822f93-e0b8-4a55-897e-42f16841a271
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480205646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_an
d_output.1480205646 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/4.kmac_sec_cm.3235278286
Short name T101
Test name
Test status
Simulation time 6671893849 ps
CPU time 104.24 seconds
Started May 21 12:53:44 PM PDT 24
Finished May 21 12:55:32 PM PDT 24
Peak memory 294332 kb
Host smart-4f4eca72-4cce-4adb-89e3-4a98fbabd39f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235278286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.3235278286 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/4.kmac_sec_cm/latest

Test location /workspace/coverage/default/4.kmac_sideload.1347009600
Short name T65
Test name
Test status
Simulation time 15397591408 ps
CPU time 383.54 seconds
Started May 21 12:53:41 PM PDT 24
Finished May 21 01:00:07 PM PDT 24
Peak memory 248144 kb
Host smart-3f170142-1448-4357-af49-261a22ea0950
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347009600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.1347009600 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_sideload/latest

Test location /workspace/coverage/default/4.kmac_smoke.2779153986
Short name T919
Test name
Test status
Simulation time 2872085700 ps
CPU time 68.21 seconds
Started May 21 12:53:42 PM PDT 24
Finished May 21 12:54:52 PM PDT 24
Peak memory 226736 kb
Host smart-dcc7f3e1-a7b6-4e4c-a9ca-a55ce8ea7b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779153986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.2779153986 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_smoke/latest

Test location /workspace/coverage/default/4.kmac_stress_all.1189447417
Short name T354
Test name
Test status
Simulation time 118424841439 ps
CPU time 736.24 seconds
Started May 21 12:53:49 PM PDT 24
Finished May 21 01:06:09 PM PDT 24
Peak memory 324536 kb
Host smart-a2ae21a3-43df-42c6-9a35-f7e5c5a539f1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1189447417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.1189447417 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_stress_all/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac.3225187107
Short name T898
Test name
Test status
Simulation time 249263966 ps
CPU time 5.82 seconds
Started May 21 12:53:34 PM PDT 24
Finished May 21 12:53:42 PM PDT 24
Peak memory 218632 kb
Host smart-911aa59e-df4b-45eb-9fb2-2bd68053900e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225187107 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.kmac_test_vectors_kmac.3225187107 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac_xof.2332049250
Short name T492
Test name
Test status
Simulation time 347999138 ps
CPU time 5.73 seconds
Started May 21 12:53:45 PM PDT 24
Finished May 21 12:53:54 PM PDT 24
Peak memory 218680 kb
Host smart-2de443cf-4140-4d99-9bad-08b8deb446c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332049250 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.kmac_test_vectors_kmac_xof.2332049250 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_224.1023056915
Short name T885
Test name
Test status
Simulation time 28823723357 ps
CPU time 2045.21 seconds
Started May 21 12:53:46 PM PDT 24
Finished May 21 01:27:55 PM PDT 24
Peak memory 389896 kb
Host smart-b37a5724-4b14-4d1d-94b8-5268111a4ef4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1023056915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.1023056915 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_256.2161779256
Short name T970
Test name
Test status
Simulation time 40364337858 ps
CPU time 1892.13 seconds
Started May 21 12:53:54 PM PDT 24
Finished May 21 01:25:31 PM PDT 24
Peak memory 390292 kb
Host smart-d40497e0-3c2e-40e9-a431-a9675aa55246
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2161779256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.2161779256 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_384.969913208
Short name T979
Test name
Test status
Simulation time 52190143579 ps
CPU time 1609.08 seconds
Started May 21 12:54:01 PM PDT 24
Finished May 21 01:20:52 PM PDT 24
Peak memory 338432 kb
Host smart-02529353-0ada-4d38-b08e-e3a7767cf3cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=969913208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.969913208 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_512.913677218
Short name T918
Test name
Test status
Simulation time 60643918642 ps
CPU time 1181.42 seconds
Started May 21 12:53:43 PM PDT 24
Finished May 21 01:13:28 PM PDT 24
Peak memory 300996 kb
Host smart-85772be9-be13-4f6a-af4c-7fbc136a5d4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=913677218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.913677218 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_128.105018308
Short name T385
Test name
Test status
Simulation time 60720484101 ps
CPU time 5038.21 seconds
Started May 21 12:53:49 PM PDT 24
Finished May 21 02:17:52 PM PDT 24
Peak memory 656420 kb
Host smart-f5e8e278-94ef-4d7c-9062-af54fc7c05ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=105018308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.105018308 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_256.214626380
Short name T292
Test name
Test status
Simulation time 53363518442 ps
CPU time 4352.82 seconds
Started May 21 12:53:29 PM PDT 24
Finished May 21 02:06:06 PM PDT 24
Peak memory 565128 kb
Host smart-7724338b-5580-4ba5-b099-70da78618cfd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=214626380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.214626380 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/40.kmac_alert_test.3922369761
Short name T776
Test name
Test status
Simulation time 44769469 ps
CPU time 0.82 seconds
Started May 21 12:58:01 PM PDT 24
Finished May 21 12:58:02 PM PDT 24
Peak memory 218532 kb
Host smart-88a994cd-1d07-4f0d-85e9-6105d3c40b7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922369761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.3922369761 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_alert_test/latest

Test location /workspace/coverage/default/40.kmac_app.4223077424
Short name T94
Test name
Test status
Simulation time 12606601371 ps
CPU time 175.95 seconds
Started May 21 12:57:57 PM PDT 24
Finished May 21 01:00:55 PM PDT 24
Peak memory 238208 kb
Host smart-fa8501c0-7316-41e1-8742-6acc129c430d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223077424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.4223077424 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_app/latest

Test location /workspace/coverage/default/40.kmac_burst_write.2807383663
Short name T230
Test name
Test status
Simulation time 8940562840 ps
CPU time 224.44 seconds
Started May 21 12:57:44 PM PDT 24
Finished May 21 01:01:29 PM PDT 24
Peak memory 228216 kb
Host smart-52cb4fc9-978d-4e03-adf5-aa6f3dc052dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807383663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.2807383663 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_burst_write/latest

Test location /workspace/coverage/default/40.kmac_entropy_refresh.4043559856
Short name T958
Test name
Test status
Simulation time 12839528368 ps
CPU time 63.78 seconds
Started May 21 12:57:57 PM PDT 24
Finished May 21 12:59:03 PM PDT 24
Peak memory 228756 kb
Host smart-1dde48b5-8fb5-409b-8fa2-d0610893cde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043559856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.4043559856 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/40.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/40.kmac_error.1846455768
Short name T411
Test name
Test status
Simulation time 9973251080 ps
CPU time 212.73 seconds
Started May 21 12:57:58 PM PDT 24
Finished May 21 01:01:32 PM PDT 24
Peak memory 258548 kb
Host smart-4c1601ca-50ed-4d0c-a345-e007e9fd93b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846455768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.1846455768 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_error/latest

Test location /workspace/coverage/default/40.kmac_key_error.1665106975
Short name T1037
Test name
Test status
Simulation time 1253824492 ps
CPU time 10.34 seconds
Started May 21 12:57:59 PM PDT 24
Finished May 21 12:58:11 PM PDT 24
Peak memory 218540 kb
Host smart-6c5f6252-5317-4093-bacc-ae78a2b49b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665106975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.1665106975 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_key_error/latest

Test location /workspace/coverage/default/40.kmac_lc_escalation.708525917
Short name T415
Test name
Test status
Simulation time 990934804 ps
CPU time 14.85 seconds
Started May 21 12:57:56 PM PDT 24
Finished May 21 12:58:12 PM PDT 24
Peak memory 240068 kb
Host smart-9d02f0f9-d80c-408a-a6c0-ee756695154b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708525917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.708525917 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/40.kmac_lc_escalation/latest

Test location /workspace/coverage/default/40.kmac_long_msg_and_output.4030210016
Short name T1007
Test name
Test status
Simulation time 105065768582 ps
CPU time 2658.13 seconds
Started May 21 12:57:43 PM PDT 24
Finished May 21 01:42:02 PM PDT 24
Peak memory 430796 kb
Host smart-412932d0-0384-4d71-8ee3-4e042574f55f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030210016 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_a
nd_output.4030210016 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/40.kmac_sideload.1686360280
Short name T603
Test name
Test status
Simulation time 15724489708 ps
CPU time 264.74 seconds
Started May 21 12:57:42 PM PDT 24
Finished May 21 01:02:08 PM PDT 24
Peak memory 246244 kb
Host smart-489f816b-013c-43c1-907d-01d8dc296b6f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686360280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.1686360280 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_sideload/latest

Test location /workspace/coverage/default/40.kmac_smoke.3202235703
Short name T489
Test name
Test status
Simulation time 1474202176 ps
CPU time 13.61 seconds
Started May 21 12:57:39 PM PDT 24
Finished May 21 12:57:54 PM PDT 24
Peak memory 226760 kb
Host smart-47e3f92a-7ffe-4c00-a0ed-c3b08cbce6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202235703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.3202235703 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_smoke/latest

Test location /workspace/coverage/default/40.kmac_stress_all.1608330738
Short name T945
Test name
Test status
Simulation time 33587517424 ps
CPU time 397.5 seconds
Started May 21 12:58:00 PM PDT 24
Finished May 21 01:04:38 PM PDT 24
Peak memory 273492 kb
Host smart-6401bb2e-3773-4ee9-8fbc-f98f40c37dcb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1608330738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.1608330738 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_stress_all/latest

Test location /workspace/coverage/default/40.kmac_stress_all_with_rand_reset.730336812
Short name T117
Test name
Test status
Simulation time 97670641396 ps
CPU time 951.99 seconds
Started May 21 12:57:58 PM PDT 24
Finished May 21 01:13:51 PM PDT 24
Peak memory 279116 kb
Host smart-75db17eb-776c-4f01-8310-5511505b7e75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=730336812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all_with_rand_reset.730336812 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac.743897914
Short name T897
Test name
Test status
Simulation time 228545557 ps
CPU time 6.44 seconds
Started May 21 12:57:53 PM PDT 24
Finished May 21 12:58:00 PM PDT 24
Peak memory 218672 kb
Host smart-e2c9e808-06d1-43f3-894c-d80a7f993bfa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743897914 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.kmac_test_vectors_kmac.743897914 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac_xof.1831911048
Short name T223
Test name
Test status
Simulation time 125084777 ps
CPU time 6.01 seconds
Started May 21 12:57:49 PM PDT 24
Finished May 21 12:57:56 PM PDT 24
Peak memory 226672 kb
Host smart-25578d6a-5e22-43d6-8aa5-e4acd8860617
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831911048 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.kmac_test_vectors_kmac_xof.1831911048 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_224.2585145078
Short name T901
Test name
Test status
Simulation time 127145631580 ps
CPU time 1834.39 seconds
Started May 21 12:57:44 PM PDT 24
Finished May 21 01:28:20 PM PDT 24
Peak memory 401744 kb
Host smart-d789a7f4-50e8-49f0-afb2-e561b69c2f45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2585145078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_224.2585145078 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_256.508265369
Short name T952
Test name
Test status
Simulation time 187616854231 ps
CPU time 2231.01 seconds
Started May 21 12:57:44 PM PDT 24
Finished May 21 01:34:55 PM PDT 24
Peak memory 380560 kb
Host smart-a3ab21cc-12c5-4eb5-ab5f-a31e59709a4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=508265369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_256.508265369 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_384.2682700006
Short name T947
Test name
Test status
Simulation time 60671013118 ps
CPU time 1715.51 seconds
Started May 21 12:57:43 PM PDT 24
Finished May 21 01:26:19 PM PDT 24
Peak memory 336596 kb
Host smart-88e64696-a6d4-4e97-9dfa-6c4701a83a66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2682700006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_384.2682700006 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_512.1104708492
Short name T903
Test name
Test status
Simulation time 46086614008 ps
CPU time 1154.34 seconds
Started May 21 12:57:51 PM PDT 24
Finished May 21 01:17:06 PM PDT 24
Peak memory 295676 kb
Host smart-ecda7397-9b11-4d0a-a12c-c5064b399be6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1104708492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_512.1104708492 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_128.3506871848
Short name T218
Test name
Test status
Simulation time 1025237127362 ps
CPU time 6194.07 seconds
Started May 21 12:57:51 PM PDT 24
Finished May 21 02:41:06 PM PDT 24
Peak memory 647508 kb
Host smart-2f7d4264-f9fc-4c96-be39-fe9195dfa106
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3506871848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_128.3506871848 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_256.2228423712
Short name T395
Test name
Test status
Simulation time 876104442921 ps
CPU time 5388.39 seconds
Started May 21 12:57:53 PM PDT 24
Finished May 21 02:27:43 PM PDT 24
Peak memory 567504 kb
Host smart-25f82d47-011c-4715-bbe3-98091eb2e968
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2228423712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_256.2228423712 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/41.kmac_alert_test.2073176146
Short name T229
Test name
Test status
Simulation time 16884860 ps
CPU time 0.8 seconds
Started May 21 12:58:15 PM PDT 24
Finished May 21 12:58:17 PM PDT 24
Peak memory 218480 kb
Host smart-2c23ff0f-a7d5-4a13-8fec-c62bb537346f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073176146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.2073176146 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_alert_test/latest

Test location /workspace/coverage/default/41.kmac_app.463325879
Short name T987
Test name
Test status
Simulation time 1518326105 ps
CPU time 31.51 seconds
Started May 21 12:58:09 PM PDT 24
Finished May 21 12:58:41 PM PDT 24
Peak memory 226996 kb
Host smart-427891a3-1dba-4595-ae14-d53c65e761a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463325879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.463325879 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_app/latest

Test location /workspace/coverage/default/41.kmac_burst_write.4223439118
Short name T1052
Test name
Test status
Simulation time 1208871279 ps
CPU time 41.07 seconds
Started May 21 12:58:03 PM PDT 24
Finished May 21 12:58:45 PM PDT 24
Peak memory 228144 kb
Host smart-2f85f182-bcc6-48ab-b23f-91e924fed7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223439118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.4223439118 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_burst_write/latest

Test location /workspace/coverage/default/41.kmac_entropy_refresh.1206949212
Short name T732
Test name
Test status
Simulation time 627878666 ps
CPU time 14.2 seconds
Started May 21 12:58:10 PM PDT 24
Finished May 21 12:58:24 PM PDT 24
Peak memory 235608 kb
Host smart-47be918f-be0a-4325-a18f-99ffc83a0ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206949212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.1206949212 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/41.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/41.kmac_error.4252437398
Short name T417
Test name
Test status
Simulation time 2916440371 ps
CPU time 126.96 seconds
Started May 21 12:58:10 PM PDT 24
Finished May 21 01:00:17 PM PDT 24
Peak memory 243156 kb
Host smart-f05fd96e-b594-4fab-816b-6abb3d6e8549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252437398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.4252437398 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_error/latest

Test location /workspace/coverage/default/41.kmac_key_error.1666602533
Short name T532
Test name
Test status
Simulation time 4225797811 ps
CPU time 8.27 seconds
Started May 21 12:58:13 PM PDT 24
Finished May 21 12:58:22 PM PDT 24
Peak memory 218600 kb
Host smart-1fd307aa-2e25-410f-8d7f-ab3aca16e769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666602533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.1666602533 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_key_error/latest

Test location /workspace/coverage/default/41.kmac_lc_escalation.546151313
Short name T66
Test name
Test status
Simulation time 48045584 ps
CPU time 1.39 seconds
Started May 21 12:58:16 PM PDT 24
Finished May 21 12:58:18 PM PDT 24
Peak memory 218632 kb
Host smart-1b6b64a2-fc34-4966-ac59-afb20075332e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546151313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.546151313 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/41.kmac_lc_escalation/latest

Test location /workspace/coverage/default/41.kmac_long_msg_and_output.2585622296
Short name T171
Test name
Test status
Simulation time 250324733905 ps
CPU time 3185.03 seconds
Started May 21 12:57:58 PM PDT 24
Finished May 21 01:51:04 PM PDT 24
Peak memory 479932 kb
Host smart-a002f816-ca92-47e1-b759-c12b3d2117a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585622296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_a
nd_output.2585622296 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/41.kmac_sideload.2961275080
Short name T753
Test name
Test status
Simulation time 62561904102 ps
CPU time 442.77 seconds
Started May 21 12:57:58 PM PDT 24
Finished May 21 01:05:22 PM PDT 24
Peak memory 248296 kb
Host smart-3d3fd20d-f2bc-42e0-a934-e1f4ea95533f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961275080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.2961275080 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_sideload/latest

Test location /workspace/coverage/default/41.kmac_smoke.3890935633
Short name T819
Test name
Test status
Simulation time 1665526419 ps
CPU time 18.72 seconds
Started May 21 12:57:57 PM PDT 24
Finished May 21 12:58:17 PM PDT 24
Peak memory 226372 kb
Host smart-5479360f-6a38-489c-82d6-7fbfdac0148a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890935633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.3890935633 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_smoke/latest

Test location /workspace/coverage/default/41.kmac_stress_all.3339632332
Short name T649
Test name
Test status
Simulation time 87514826907 ps
CPU time 564.7 seconds
Started May 21 12:58:15 PM PDT 24
Finished May 21 01:07:40 PM PDT 24
Peak memory 286816 kb
Host smart-d9470ff5-0e1a-4084-9941-2d92a1f19d24
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3339632332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.3339632332 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_stress_all/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac.2573805924
Short name T450
Test name
Test status
Simulation time 986132449 ps
CPU time 6.73 seconds
Started May 21 12:58:04 PM PDT 24
Finished May 21 12:58:12 PM PDT 24
Peak memory 218632 kb
Host smart-435a3cd1-44c0-42f1-8390-324d07a0d6b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573805924 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.kmac_test_vectors_kmac.2573805924 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac_xof.1768708837
Short name T854
Test name
Test status
Simulation time 104810545 ps
CPU time 6.27 seconds
Started May 21 12:58:03 PM PDT 24
Finished May 21 12:58:10 PM PDT 24
Peak memory 226692 kb
Host smart-6e64ff4c-a065-4e67-8d78-6521c872484b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768708837 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.kmac_test_vectors_kmac_xof.1768708837 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_224.4280454245
Short name T318
Test name
Test status
Simulation time 21338112593 ps
CPU time 2129.49 seconds
Started May 21 12:58:02 PM PDT 24
Finished May 21 01:33:33 PM PDT 24
Peak memory 402444 kb
Host smart-8cd7b635-dfe4-40c4-bf4f-280f8dd005b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4280454245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_224.4280454245 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_256.318375846
Short name T212
Test name
Test status
Simulation time 193356879651 ps
CPU time 2289.32 seconds
Started May 21 12:58:04 PM PDT 24
Finished May 21 01:36:14 PM PDT 24
Peak memory 397596 kb
Host smart-f1fcfaf5-7909-4265-9b72-f64dadd42c40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=318375846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_256.318375846 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_384.1261901320
Short name T785
Test name
Test status
Simulation time 106529024988 ps
CPU time 1448.45 seconds
Started May 21 12:57:59 PM PDT 24
Finished May 21 01:22:09 PM PDT 24
Peak memory 337040 kb
Host smart-f7b0bd24-ce14-4227-af24-95b6fe02cb23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1261901320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_384.1261901320 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_512.3045790558
Short name T821
Test name
Test status
Simulation time 176319118785 ps
CPU time 1179.29 seconds
Started May 21 12:58:03 PM PDT 24
Finished May 21 01:17:43 PM PDT 24
Peak memory 301740 kb
Host smart-4428854d-11d4-4704-b7ab-7ea5784808c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3045790558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_512.3045790558 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_128.579062274
Short name T680
Test name
Test status
Simulation time 136046881312 ps
CPU time 5420.93 seconds
Started May 21 12:58:02 PM PDT 24
Finished May 21 02:28:25 PM PDT 24
Peak memory 670732 kb
Host smart-cb915ce9-8ac4-4c91-a799-315cf72ad1b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=579062274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_128.579062274 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_256.783897911
Short name T726
Test name
Test status
Simulation time 223110883940 ps
CPU time 4180.5 seconds
Started May 21 12:58:02 PM PDT 24
Finished May 21 02:07:44 PM PDT 24
Peak memory 574432 kb
Host smart-a501d59f-dfef-4336-903c-16a39b4fc53c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=783897911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_256.783897911 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/42.kmac_alert_test.3195949968
Short name T444
Test name
Test status
Simulation time 15781319 ps
CPU time 0.85 seconds
Started May 21 12:58:35 PM PDT 24
Finished May 21 12:58:36 PM PDT 24
Peak memory 218536 kb
Host smart-d11e7968-9b42-45c7-8133-dec3a5e1b66c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195949968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.3195949968 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_alert_test/latest

Test location /workspace/coverage/default/42.kmac_app.390109653
Short name T747
Test name
Test status
Simulation time 13600217958 ps
CPU time 89.61 seconds
Started May 21 12:58:27 PM PDT 24
Finished May 21 12:59:57 PM PDT 24
Peak memory 231532 kb
Host smart-76210d97-49da-451e-afb0-63c4049b5462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390109653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.390109653 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_app/latest

Test location /workspace/coverage/default/42.kmac_burst_write.301341290
Short name T37
Test name
Test status
Simulation time 10443054293 ps
CPU time 472.94 seconds
Started May 21 12:58:13 PM PDT 24
Finished May 21 01:06:06 PM PDT 24
Peak memory 239544 kb
Host smart-4f07405f-b33a-40df-82bc-905b85547bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301341290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.301341290 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_burst_write/latest

Test location /workspace/coverage/default/42.kmac_entropy_refresh.3075103381
Short name T314
Test name
Test status
Simulation time 92396925910 ps
CPU time 107.18 seconds
Started May 21 12:58:25 PM PDT 24
Finished May 21 01:00:13 PM PDT 24
Peak memory 242036 kb
Host smart-a0dc4fc2-b3a9-4dc0-baa9-bf888ad6fd3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075103381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.3075103381 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/42.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/42.kmac_error.1322132082
Short name T339
Test name
Test status
Simulation time 39306195705 ps
CPU time 323.78 seconds
Started May 21 12:58:31 PM PDT 24
Finished May 21 01:03:56 PM PDT 24
Peak memory 259528 kb
Host smart-ca2970df-297f-4edf-9905-84d3fa3946f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322132082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.1322132082 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_error/latest

Test location /workspace/coverage/default/42.kmac_key_error.260354233
Short name T530
Test name
Test status
Simulation time 1064226015 ps
CPU time 7.55 seconds
Started May 21 12:58:32 PM PDT 24
Finished May 21 12:58:40 PM PDT 24
Peak memory 218508 kb
Host smart-5f5badd4-35dc-4cc2-9f79-50e7d26b9d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260354233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.260354233 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_key_error/latest

Test location /workspace/coverage/default/42.kmac_lc_escalation.3806942227
Short name T629
Test name
Test status
Simulation time 56112256 ps
CPU time 1.24 seconds
Started May 21 12:58:32 PM PDT 24
Finished May 21 12:58:34 PM PDT 24
Peak memory 218664 kb
Host smart-f34da43a-1ef0-4122-9d64-df9b257adb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806942227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.3806942227 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/42.kmac_lc_escalation/latest

Test location /workspace/coverage/default/42.kmac_long_msg_and_output.2278559715
Short name T902
Test name
Test status
Simulation time 174024751819 ps
CPU time 2258.92 seconds
Started May 21 12:58:14 PM PDT 24
Finished May 21 01:35:53 PM PDT 24
Peak memory 398336 kb
Host smart-1a6a8a54-18a6-4802-92db-8efa817f24cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278559715 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_a
nd_output.2278559715 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/42.kmac_sideload.1265058134
Short name T733
Test name
Test status
Simulation time 3183748227 ps
CPU time 263.35 seconds
Started May 21 12:58:14 PM PDT 24
Finished May 21 01:02:38 PM PDT 24
Peak memory 242764 kb
Host smart-d83fad48-3d09-4fec-8adc-c3ec68a1dc44
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265058134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.1265058134 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_sideload/latest

Test location /workspace/coverage/default/42.kmac_smoke.1160134758
Short name T316
Test name
Test status
Simulation time 1303150708 ps
CPU time 21.87 seconds
Started May 21 12:58:14 PM PDT 24
Finished May 21 12:58:37 PM PDT 24
Peak memory 226128 kb
Host smart-6a9c97d7-2a56-4f27-888b-52b544ba210d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160134758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.1160134758 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_smoke/latest

Test location /workspace/coverage/default/42.kmac_stress_all.1311234277
Short name T582
Test name
Test status
Simulation time 2522649517 ps
CPU time 121.54 seconds
Started May 21 12:58:31 PM PDT 24
Finished May 21 01:00:33 PM PDT 24
Peak memory 251592 kb
Host smart-7de1c315-277f-4015-a392-7898f5562728
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1311234277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.1311234277 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_stress_all/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac.3586618640
Short name T645
Test name
Test status
Simulation time 432459192 ps
CPU time 7.01 seconds
Started May 21 12:58:26 PM PDT 24
Finished May 21 12:58:34 PM PDT 24
Peak memory 218572 kb
Host smart-181b07ec-d058-44ad-b74a-cbde878d4596
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586618640 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.kmac_test_vectors_kmac.3586618640 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac_xof.2822986221
Short name T581
Test name
Test status
Simulation time 1244988231 ps
CPU time 6.54 seconds
Started May 21 12:58:25 PM PDT 24
Finished May 21 12:58:33 PM PDT 24
Peak memory 226660 kb
Host smart-da00b74c-8945-4a20-b7b6-40a30ecaf925
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822986221 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.kmac_test_vectors_kmac_xof.2822986221 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_224.1465015769
Short name T428
Test name
Test status
Simulation time 92403751874 ps
CPU time 2126.49 seconds
Started May 21 12:58:19 PM PDT 24
Finished May 21 01:33:47 PM PDT 24
Peak memory 397404 kb
Host smart-fa903e6c-0e05-40f9-a745-b8f6f44e15f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1465015769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_224.1465015769 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_256.433514616
Short name T1040
Test name
Test status
Simulation time 771134555491 ps
CPU time 2138.4 seconds
Started May 21 12:58:21 PM PDT 24
Finished May 21 01:34:01 PM PDT 24
Peak memory 389196 kb
Host smart-5023d2d4-74fe-490a-bff4-de9aea48b0ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=433514616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_256.433514616 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_384.3641786097
Short name T326
Test name
Test status
Simulation time 16217055368 ps
CPU time 1601.9 seconds
Started May 21 12:58:22 PM PDT 24
Finished May 21 01:25:05 PM PDT 24
Peak memory 339328 kb
Host smart-e77ac698-80e0-4b83-9d3e-a5b4b5f9be9c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3641786097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_384.3641786097 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_512.3134536035
Short name T345
Test name
Test status
Simulation time 193063328380 ps
CPU time 1386.02 seconds
Started May 21 12:58:20 PM PDT 24
Finished May 21 01:21:27 PM PDT 24
Peak memory 298264 kb
Host smart-d881aed5-c3cf-466e-99e2-435123f81f16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3134536035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_512.3134536035 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_shake_128.2205634367
Short name T600
Test name
Test status
Simulation time 191561850448 ps
CPU time 5770.58 seconds
Started May 21 12:58:21 PM PDT 24
Finished May 21 02:34:33 PM PDT 24
Peak memory 667560 kb
Host smart-2d9a9723-6756-4f72-94a3-159e32d39ba9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2205634367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_128.2205634367 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_shake_256.4123004944
Short name T378
Test name
Test status
Simulation time 227486031674 ps
CPU time 4150.63 seconds
Started May 21 12:58:26 PM PDT 24
Finished May 21 02:07:38 PM PDT 24
Peak memory 573136 kb
Host smart-a19988bc-a396-4eba-b3f7-c63456d378b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4123004944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_256.4123004944 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/43.kmac_alert_test.1774837727
Short name T628
Test name
Test status
Simulation time 22718853 ps
CPU time 0.94 seconds
Started May 21 12:59:01 PM PDT 24
Finished May 21 12:59:03 PM PDT 24
Peak memory 220560 kb
Host smart-c2860035-31c3-4437-92d4-1c3f5e6325f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774837727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.1774837727 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_alert_test/latest

Test location /workspace/coverage/default/43.kmac_app.3278581581
Short name T156
Test name
Test status
Simulation time 6633092722 ps
CPU time 198.17 seconds
Started May 21 12:58:57 PM PDT 24
Finished May 21 01:02:16 PM PDT 24
Peak memory 239840 kb
Host smart-387cb8bf-81c4-4428-bfff-3595d03485b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278581581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.3278581581 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_app/latest

Test location /workspace/coverage/default/43.kmac_burst_write.1152435574
Short name T922
Test name
Test status
Simulation time 6143037235 ps
CPU time 196.4 seconds
Started May 21 12:58:44 PM PDT 24
Finished May 21 01:02:01 PM PDT 24
Peak memory 228832 kb
Host smart-68d244b9-057c-47fd-bfdc-4abe55a7358d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152435574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.1152435574 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_burst_write/latest

Test location /workspace/coverage/default/43.kmac_entropy_refresh.1495787388
Short name T70
Test name
Test status
Simulation time 5718736229 ps
CPU time 215.35 seconds
Started May 21 12:58:56 PM PDT 24
Finished May 21 01:02:31 PM PDT 24
Peak memory 241416 kb
Host smart-01ab2fb1-3cd6-4b07-b331-dd2e8c0f06af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495787388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.1495787388 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/43.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/43.kmac_error.58104760
Short name T926
Test name
Test status
Simulation time 4191438531 ps
CPU time 187.12 seconds
Started May 21 12:59:02 PM PDT 24
Finished May 21 01:02:10 PM PDT 24
Peak memory 251312 kb
Host smart-ec79e44e-8c1b-488f-9dca-1592034535c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58104760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.58104760 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_error/latest

Test location /workspace/coverage/default/43.kmac_key_error.3474132955
Short name T899
Test name
Test status
Simulation time 1483041982 ps
CPU time 4.53 seconds
Started May 21 12:59:03 PM PDT 24
Finished May 21 12:59:08 PM PDT 24
Peak memory 218448 kb
Host smart-ecc284e4-1dc2-47f4-89fb-c9285c3fc1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474132955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.3474132955 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_key_error/latest

Test location /workspace/coverage/default/43.kmac_lc_escalation.497611885
Short name T47
Test name
Test status
Simulation time 45638296 ps
CPU time 1.43 seconds
Started May 21 12:59:02 PM PDT 24
Finished May 21 12:59:04 PM PDT 24
Peak memory 218696 kb
Host smart-40879005-49ef-4ca2-9c2c-6a7a4790ee2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497611885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.497611885 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/43.kmac_lc_escalation/latest

Test location /workspace/coverage/default/43.kmac_long_msg_and_output.913581787
Short name T955
Test name
Test status
Simulation time 2589535557 ps
CPU time 298.15 seconds
Started May 21 12:58:36 PM PDT 24
Finished May 21 01:03:34 PM PDT 24
Peak memory 246056 kb
Host smart-913123eb-dd7f-47f6-a284-376065959fa8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913581787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_an
d_output.913581787 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/43.kmac_sideload.1617608192
Short name T667
Test name
Test status
Simulation time 1291423366 ps
CPU time 28.66 seconds
Started May 21 12:58:38 PM PDT 24
Finished May 21 12:59:07 PM PDT 24
Peak memory 223688 kb
Host smart-99f1a74f-2743-4262-8f05-cca3a0b0e034
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617608192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.1617608192 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_sideload/latest

Test location /workspace/coverage/default/43.kmac_smoke.2631227957
Short name T1049
Test name
Test status
Simulation time 6154854381 ps
CPU time 86 seconds
Started May 21 12:58:38 PM PDT 24
Finished May 21 01:00:04 PM PDT 24
Peak memory 222736 kb
Host smart-278b9384-dc29-4676-b49f-024aa0a64739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631227957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.2631227957 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_smoke/latest

Test location /workspace/coverage/default/43.kmac_stress_all.2829092447
Short name T336
Test name
Test status
Simulation time 47223756730 ps
CPU time 1501.19 seconds
Started May 21 12:59:03 PM PDT 24
Finished May 21 01:24:05 PM PDT 24
Peak memory 350868 kb
Host smart-54052808-a608-475a-8bc3-7c5247947a18
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2829092447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.2829092447 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_stress_all/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac.3884731769
Short name T526
Test name
Test status
Simulation time 1606663839 ps
CPU time 6.18 seconds
Started May 21 12:58:58 PM PDT 24
Finished May 21 12:59:04 PM PDT 24
Peak memory 219572 kb
Host smart-0207344a-a4a1-4ca6-b2fb-6f724b2a4377
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884731769 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.kmac_test_vectors_kmac.3884731769 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac_xof.2564103991
Short name T676
Test name
Test status
Simulation time 307048273 ps
CPU time 6.77 seconds
Started May 21 12:58:58 PM PDT 24
Finished May 21 12:59:05 PM PDT 24
Peak memory 226676 kb
Host smart-9a910620-32fa-4446-a324-bb93bf3f9ff6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564103991 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.kmac_test_vectors_kmac_xof.2564103991 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_224.4116230797
Short name T511
Test name
Test status
Simulation time 384432561253 ps
CPU time 2318.89 seconds
Started May 21 12:58:43 PM PDT 24
Finished May 21 01:37:23 PM PDT 24
Peak memory 394852 kb
Host smart-c797754e-a533-47ba-9479-9447212f732f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4116230797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_224.4116230797 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_256.2681123925
Short name T906
Test name
Test status
Simulation time 243173013413 ps
CPU time 1875.92 seconds
Started May 21 12:58:44 PM PDT 24
Finished May 21 01:30:00 PM PDT 24
Peak memory 391964 kb
Host smart-086f5cac-d2e7-4ca8-92e3-faf80859a0bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2681123925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_256.2681123925 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_384.2865348225
Short name T438
Test name
Test status
Simulation time 787135749634 ps
CPU time 1934.92 seconds
Started May 21 12:58:50 PM PDT 24
Finished May 21 01:31:06 PM PDT 24
Peak memory 338984 kb
Host smart-0f0ac2cb-b72c-43f5-a10f-1c5eff8bd35b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2865348225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_384.2865348225 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_512.2560265177
Short name T623
Test name
Test status
Simulation time 46850554581 ps
CPU time 1298.59 seconds
Started May 21 12:58:49 PM PDT 24
Finished May 21 01:20:28 PM PDT 24
Peak memory 303332 kb
Host smart-66179921-f0d2-491c-9d6f-0ff9b755a095
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2560265177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_512.2560265177 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_128.686636517
Short name T677
Test name
Test status
Simulation time 949529728847 ps
CPU time 5701.22 seconds
Started May 21 12:58:49 PM PDT 24
Finished May 21 02:33:52 PM PDT 24
Peak memory 664828 kb
Host smart-27d4094d-172c-4a68-8aad-9756a5307761
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=686636517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_128.686636517 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_256.2209174098
Short name T755
Test name
Test status
Simulation time 475747910386 ps
CPU time 5198.19 seconds
Started May 21 12:58:48 PM PDT 24
Finished May 21 02:25:28 PM PDT 24
Peak memory 573100 kb
Host smart-1372c38c-2259-4105-9084-94485f3d0f3d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2209174098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_256.2209174098 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/44.kmac_alert_test.337495967
Short name T472
Test name
Test status
Simulation time 44149198 ps
CPU time 0.92 seconds
Started May 21 12:59:20 PM PDT 24
Finished May 21 12:59:21 PM PDT 24
Peak memory 218452 kb
Host smart-625661a5-7de1-44b0-8ba4-c68be2bf6c8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337495967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.337495967 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/44.kmac_alert_test/latest

Test location /workspace/coverage/default/44.kmac_app.865335125
Short name T293
Test name
Test status
Simulation time 5714675776 ps
CPU time 412.76 seconds
Started May 21 12:59:19 PM PDT 24
Finished May 21 01:06:13 PM PDT 24
Peak memory 250756 kb
Host smart-635ba5a7-af08-4367-a250-3315b757a408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865335125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.865335125 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_app/latest

Test location /workspace/coverage/default/44.kmac_burst_write.1403703451
Short name T601
Test name
Test status
Simulation time 13543716191 ps
CPU time 767.22 seconds
Started May 21 12:59:08 PM PDT 24
Finished May 21 01:11:56 PM PDT 24
Peak memory 234980 kb
Host smart-acfe2592-32bb-40b6-ba49-e27d7af55633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403703451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.1403703451 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_burst_write/latest

Test location /workspace/coverage/default/44.kmac_entropy_refresh.2604747931
Short name T384
Test name
Test status
Simulation time 8690290429 ps
CPU time 389.3 seconds
Started May 21 12:59:18 PM PDT 24
Finished May 21 01:05:48 PM PDT 24
Peak memory 250904 kb
Host smart-16b7c70f-db9f-41bd-9102-b423e831fd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604747931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.2604747931 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/44.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/44.kmac_error.2843592172
Short name T1024
Test name
Test status
Simulation time 41768193921 ps
CPU time 300.3 seconds
Started May 21 12:59:19 PM PDT 24
Finished May 21 01:04:20 PM PDT 24
Peak memory 259440 kb
Host smart-941d1c57-3f5f-4228-8573-d01e10ad86dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843592172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.2843592172 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_error/latest

Test location /workspace/coverage/default/44.kmac_key_error.3621782701
Short name T99
Test name
Test status
Simulation time 1995580407 ps
CPU time 8.55 seconds
Started May 21 12:59:20 PM PDT 24
Finished May 21 12:59:29 PM PDT 24
Peak memory 218448 kb
Host smart-ca53b674-d9cb-4a66-928f-c8083b7e92ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621782701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.3621782701 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_key_error/latest

Test location /workspace/coverage/default/44.kmac_lc_escalation.577206836
Short name T31
Test name
Test status
Simulation time 67515920 ps
CPU time 1.24 seconds
Started May 21 12:59:20 PM PDT 24
Finished May 21 12:59:22 PM PDT 24
Peak memory 218728 kb
Host smart-74f56674-d056-4f3d-b00f-c41b881c273c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577206836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.577206836 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/44.kmac_lc_escalation/latest

Test location /workspace/coverage/default/44.kmac_long_msg_and_output.3825735013
Short name T675
Test name
Test status
Simulation time 241604562823 ps
CPU time 1818.87 seconds
Started May 21 12:59:11 PM PDT 24
Finished May 21 01:29:31 PM PDT 24
Peak memory 355004 kb
Host smart-dbf4393a-5bc1-4a8f-923d-9c89946f5ecc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825735013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_a
nd_output.3825735013 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/44.kmac_sideload.2336396293
Short name T643
Test name
Test status
Simulation time 12066992982 ps
CPU time 442.98 seconds
Started May 21 12:59:12 PM PDT 24
Finished May 21 01:06:35 PM PDT 24
Peak memory 253040 kb
Host smart-7fbdad9d-aca9-49eb-8505-1a7503489338
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336396293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.2336396293 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_sideload/latest

Test location /workspace/coverage/default/44.kmac_smoke.2092714113
Short name T664
Test name
Test status
Simulation time 22100637912 ps
CPU time 25.86 seconds
Started May 21 12:59:03 PM PDT 24
Finished May 21 12:59:30 PM PDT 24
Peak memory 226724 kb
Host smart-de7e4893-0341-4dd5-a0dc-1790da9f5910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092714113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.2092714113 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_smoke/latest

Test location /workspace/coverage/default/44.kmac_stress_all.4121469920
Short name T887
Test name
Test status
Simulation time 86557517993 ps
CPU time 207.62 seconds
Started May 21 12:59:20 PM PDT 24
Finished May 21 01:02:49 PM PDT 24
Peak memory 253036 kb
Host smart-00454f85-85d1-4ad7-9b56-a2bf77f7137c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4121469920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.4121469920 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_stress_all/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac.172697401
Short name T460
Test name
Test status
Simulation time 916724254 ps
CPU time 5.98 seconds
Started May 21 12:59:13 PM PDT 24
Finished May 21 12:59:19 PM PDT 24
Peak memory 219540 kb
Host smart-77d50753-b4a1-45ee-8440-5a1395291c9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172697401 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.kmac_test_vectors_kmac.172697401 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac_xof.920202148
Short name T320
Test name
Test status
Simulation time 860849233 ps
CPU time 5.64 seconds
Started May 21 12:59:12 PM PDT 24
Finished May 21 12:59:18 PM PDT 24
Peak memory 226648 kb
Host smart-b4859e4e-2ee9-4b72-b64b-bb7fe77a80cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920202148 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.kmac_test_vectors_kmac_xof.920202148 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_224.1827042184
Short name T2
Test name
Test status
Simulation time 280163284171 ps
CPU time 1931.17 seconds
Started May 21 12:59:12 PM PDT 24
Finished May 21 01:31:24 PM PDT 24
Peak memory 394068 kb
Host smart-b83401e6-f9bf-440b-8f61-ec682fb39339
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1827042184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_224.1827042184 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_256.4237652992
Short name T736
Test name
Test status
Simulation time 67446408546 ps
CPU time 1685.21 seconds
Started May 21 12:59:08 PM PDT 24
Finished May 21 01:27:14 PM PDT 24
Peak memory 379904 kb
Host smart-b5af4038-c42c-42f1-868c-54168129aad1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4237652992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_256.4237652992 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_384.3441181323
Short name T743
Test name
Test status
Simulation time 14802929342 ps
CPU time 1682.68 seconds
Started May 21 12:59:11 PM PDT 24
Finished May 21 01:27:14 PM PDT 24
Peak memory 340196 kb
Host smart-af1f421b-265c-40b5-8f5d-b2444dcc20bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3441181323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_384.3441181323 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_512.720838310
Short name T789
Test name
Test status
Simulation time 10495771249 ps
CPU time 1143.95 seconds
Started May 21 12:59:13 PM PDT 24
Finished May 21 01:18:17 PM PDT 24
Peak memory 296540 kb
Host smart-8ea5c396-8d8b-41b5-a559-58f187e90ac6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=720838310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_512.720838310 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_shake_128.2029316210
Short name T572
Test name
Test status
Simulation time 81757641619 ps
CPU time 5157.75 seconds
Started May 21 12:59:13 PM PDT 24
Finished May 21 02:25:12 PM PDT 24
Peak memory 655728 kb
Host smart-48975f50-3986-47fb-bbad-e8072efc0f24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2029316210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_128.2029316210 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_shake_256.1072933451
Short name T839
Test name
Test status
Simulation time 1016285873646 ps
CPU time 5365.71 seconds
Started May 21 12:59:23 PM PDT 24
Finished May 21 02:28:49 PM PDT 24
Peak memory 583140 kb
Host smart-331f6c26-8a9e-4f59-ab97-80166ef06b93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1072933451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_256.1072933451 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/45.kmac_alert_test.68439948
Short name T911
Test name
Test status
Simulation time 15048898 ps
CPU time 0.83 seconds
Started May 21 12:59:43 PM PDT 24
Finished May 21 12:59:44 PM PDT 24
Peak memory 218712 kb
Host smart-151e930c-3cb4-45a3-a0ba-08ff5813e244
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68439948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.68439948 +enable_mas
king=1 +sw_key_masked=0
Directory /workspace/45.kmac_alert_test/latest

Test location /workspace/coverage/default/45.kmac_app.2206193898
Short name T773
Test name
Test status
Simulation time 11210171209 ps
CPU time 342.62 seconds
Started May 21 12:59:39 PM PDT 24
Finished May 21 01:05:22 PM PDT 24
Peak memory 252596 kb
Host smart-f68dac07-5a37-4a66-a861-7fd453acf2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206193898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.2206193898 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_app/latest

Test location /workspace/coverage/default/45.kmac_burst_write.3146294622
Short name T681
Test name
Test status
Simulation time 56860609184 ps
CPU time 1489.45 seconds
Started May 21 12:59:26 PM PDT 24
Finished May 21 01:24:16 PM PDT 24
Peak memory 237256 kb
Host smart-98be798d-15da-4c92-8750-d81d2c9a6238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146294622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.3146294622 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_burst_write/latest

Test location /workspace/coverage/default/45.kmac_error.1848847258
Short name T991
Test name
Test status
Simulation time 23953590151 ps
CPU time 374.74 seconds
Started May 21 12:59:38 PM PDT 24
Finished May 21 01:05:53 PM PDT 24
Peak memory 262628 kb
Host smart-6084396e-5952-4e78-aad4-d5213f31d15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848847258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.1848847258 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_error/latest

Test location /workspace/coverage/default/45.kmac_key_error.2971076220
Short name T981
Test name
Test status
Simulation time 364669764 ps
CPU time 3.29 seconds
Started May 21 12:59:45 PM PDT 24
Finished May 21 12:59:49 PM PDT 24
Peak memory 218524 kb
Host smart-1b0d46fe-a4eb-4a0d-8a07-f073f2f458f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971076220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.2971076220 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_key_error/latest

Test location /workspace/coverage/default/45.kmac_lc_escalation.3044909010
Short name T55
Test name
Test status
Simulation time 67971444 ps
CPU time 1.38 seconds
Started May 21 12:59:44 PM PDT 24
Finished May 21 12:59:46 PM PDT 24
Peak memory 218704 kb
Host smart-a5f031c1-7194-4ec1-b509-ccd816d6d99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044909010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.3044909010 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/45.kmac_lc_escalation/latest

Test location /workspace/coverage/default/45.kmac_long_msg_and_output.3011423946
Short name T957
Test name
Test status
Simulation time 31429971560 ps
CPU time 104.21 seconds
Started May 21 12:59:18 PM PDT 24
Finished May 21 01:01:03 PM PDT 24
Peak memory 226932 kb
Host smart-fd86e0b1-937a-4805-8df3-8b09f0bf6c08
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011423946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_a
nd_output.3011423946 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/45.kmac_sideload.3501104941
Short name T471
Test name
Test status
Simulation time 1192148841 ps
CPU time 14.56 seconds
Started May 21 12:59:19 PM PDT 24
Finished May 21 12:59:34 PM PDT 24
Peak memory 226752 kb
Host smart-a0c6b67a-c712-4513-a5de-176ef0ae7fff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501104941 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.3501104941 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_sideload/latest

Test location /workspace/coverage/default/45.kmac_smoke.2485650
Short name T1061
Test name
Test status
Simulation time 122207600 ps
CPU time 5 seconds
Started May 21 12:59:19 PM PDT 24
Finished May 21 12:59:24 PM PDT 24
Peak memory 226568 kb
Host smart-fa787bc0-5a2a-4ba9-a439-f85c9ed0e0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.2485650 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_smoke/latest

Test location /workspace/coverage/default/45.kmac_stress_all.2270044925
Short name T541
Test name
Test status
Simulation time 57102410028 ps
CPU time 876.41 seconds
Started May 21 12:59:43 PM PDT 24
Finished May 21 01:14:20 PM PDT 24
Peak memory 342144 kb
Host smart-adc1439d-2669-4b5a-8442-8338e932a676
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2270044925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.2270044925 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_stress_all/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac.309807033
Short name T241
Test name
Test status
Simulation time 359819404 ps
CPU time 5.32 seconds
Started May 21 12:59:32 PM PDT 24
Finished May 21 12:59:38 PM PDT 24
Peak memory 218644 kb
Host smart-d6bf0586-2832-4625-b6ec-ad1f15924da8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309807033 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.kmac_test_vectors_kmac.309807033 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac_xof.3504950833
Short name T280
Test name
Test status
Simulation time 440455375 ps
CPU time 5.66 seconds
Started May 21 12:59:37 PM PDT 24
Finished May 21 12:59:43 PM PDT 24
Peak memory 219628 kb
Host smart-2bb357fa-f037-49ec-b644-068fc8f7c8e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504950833 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.kmac_test_vectors_kmac_xof.3504950833 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_224.3855762422
Short name T674
Test name
Test status
Simulation time 611928046633 ps
CPU time 2275.45 seconds
Started May 21 12:59:26 PM PDT 24
Finished May 21 01:37:22 PM PDT 24
Peak memory 402432 kb
Host smart-f9da0b50-3f07-4fac-b222-aec575d8ab0f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3855762422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_224.3855762422 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_256.1157604464
Short name T779
Test name
Test status
Simulation time 322443438375 ps
CPU time 2240.53 seconds
Started May 21 12:59:26 PM PDT 24
Finished May 21 01:36:47 PM PDT 24
Peak memory 381940 kb
Host smart-14786f2e-16f0-44b6-8d48-7d17e71b3421
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1157604464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_256.1157604464 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_384.267691095
Short name T711
Test name
Test status
Simulation time 281037408298 ps
CPU time 1789.14 seconds
Started May 21 12:59:31 PM PDT 24
Finished May 21 01:29:21 PM PDT 24
Peak memory 338620 kb
Host smart-6075e4fe-5dee-4e57-93de-f95a7dc7bc15
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=267691095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_384.267691095 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_512.3906124817
Short name T539
Test name
Test status
Simulation time 11296015965 ps
CPU time 1153.89 seconds
Started May 21 12:59:34 PM PDT 24
Finished May 21 01:18:49 PM PDT 24
Peak memory 298968 kb
Host smart-3c82a5c4-762e-4259-99c5-2cc2cb8495ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3906124817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_512.3906124817 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_shake_128.4071981159
Short name T739
Test name
Test status
Simulation time 1450097031311 ps
CPU time 6593.02 seconds
Started May 21 12:59:32 PM PDT 24
Finished May 21 02:49:26 PM PDT 24
Peak memory 666340 kb
Host smart-cb4658c0-0318-4e1f-92f8-53d96ff9b029
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4071981159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_128.4071981159 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_shake_256.249008165
Short name T826
Test name
Test status
Simulation time 56077362560 ps
CPU time 4480.82 seconds
Started May 21 12:59:35 PM PDT 24
Finished May 21 02:14:17 PM PDT 24
Peak memory 576348 kb
Host smart-9b974c89-a7be-4ce2-8f99-7416cb04a565
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=249008165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_256.249008165 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/46.kmac_alert_test.1859701312
Short name T588
Test name
Test status
Simulation time 26959797 ps
CPU time 0.87 seconds
Started May 21 12:59:55 PM PDT 24
Finished May 21 12:59:57 PM PDT 24
Peak memory 218528 kb
Host smart-d221e686-52ce-4fb0-bf4b-af571a143f89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859701312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.1859701312 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_alert_test/latest

Test location /workspace/coverage/default/46.kmac_app.1934656588
Short name T157
Test name
Test status
Simulation time 89680998468 ps
CPU time 248.84 seconds
Started May 21 01:00:00 PM PDT 24
Finished May 21 01:04:09 PM PDT 24
Peak memory 242116 kb
Host smart-ad85a273-9e1c-41e0-94c0-2e0b0e9841d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934656588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.1934656588 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_app/latest

Test location /workspace/coverage/default/46.kmac_burst_write.941378506
Short name T505
Test name
Test status
Simulation time 93178112947 ps
CPU time 1201.58 seconds
Started May 21 12:59:52 PM PDT 24
Finished May 21 01:19:54 PM PDT 24
Peak memory 237136 kb
Host smart-b6b39b86-4743-40e5-aef9-7bf3342bcf54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941378506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.941378506 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_burst_write/latest

Test location /workspace/coverage/default/46.kmac_entropy_refresh.635713324
Short name T1068
Test name
Test status
Simulation time 51545042344 ps
CPU time 226.93 seconds
Started May 21 12:59:54 PM PDT 24
Finished May 21 01:03:41 PM PDT 24
Peak memory 243360 kb
Host smart-d37dd0fd-fd1e-4aac-a621-32025d82d124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635713324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.635713324 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/46.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/46.kmac_error.4013264271
Short name T689
Test name
Test status
Simulation time 20189343009 ps
CPU time 124.78 seconds
Started May 21 12:59:54 PM PDT 24
Finished May 21 01:02:00 PM PDT 24
Peak memory 243248 kb
Host smart-35e1fa77-747a-4e87-9aa0-2f3866817e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013264271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.4013264271 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_error/latest

Test location /workspace/coverage/default/46.kmac_key_error.99868960
Short name T97
Test name
Test status
Simulation time 3735314280 ps
CPU time 5.61 seconds
Started May 21 01:00:00 PM PDT 24
Finished May 21 01:00:06 PM PDT 24
Peak memory 218508 kb
Host smart-2c0496d4-c686-4ae2-b640-4db1a1279678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99868960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.99868960 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_key_error/latest

Test location /workspace/coverage/default/46.kmac_lc_escalation.252911886
Short name T257
Test name
Test status
Simulation time 62237255 ps
CPU time 1.52 seconds
Started May 21 01:00:00 PM PDT 24
Finished May 21 01:00:03 PM PDT 24
Peak memory 218696 kb
Host smart-ecf6c885-1220-47de-ac2a-6e904465053c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252911886 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.252911886 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/46.kmac_lc_escalation/latest

Test location /workspace/coverage/default/46.kmac_long_msg_and_output.1020168305
Short name T1069
Test name
Test status
Simulation time 65684307715 ps
CPU time 2214.05 seconds
Started May 21 12:59:43 PM PDT 24
Finished May 21 01:36:39 PM PDT 24
Peak memory 405976 kb
Host smart-3f75636c-03a9-4219-ad02-07ca109074ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020168305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_a
nd_output.1020168305 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/46.kmac_sideload.222438781
Short name T790
Test name
Test status
Simulation time 29782734199 ps
CPU time 513.64 seconds
Started May 21 12:59:49 PM PDT 24
Finished May 21 01:08:24 PM PDT 24
Peak memory 257236 kb
Host smart-f5ad45fc-244a-49b4-b1ee-2c2ec5b097d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222438781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.222438781 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_sideload/latest

Test location /workspace/coverage/default/46.kmac_smoke.2541373507
Short name T646
Test name
Test status
Simulation time 1390341568 ps
CPU time 45.13 seconds
Started May 21 12:59:44 PM PDT 24
Finished May 21 01:00:29 PM PDT 24
Peak memory 218536 kb
Host smart-bb12d63b-081d-43ab-8fcd-6fcfc04871d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541373507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.2541373507 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_smoke/latest

Test location /workspace/coverage/default/46.kmac_stress_all.541952995
Short name T398
Test name
Test status
Simulation time 17952542662 ps
CPU time 1550.27 seconds
Started May 21 12:59:58 PM PDT 24
Finished May 21 01:25:49 PM PDT 24
Peak memory 347056 kb
Host smart-188d3f08-2f00-4047-9920-19a44b238217
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=541952995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.541952995 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_stress_all/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac.3798825728
Short name T754
Test name
Test status
Simulation time 668416231 ps
CPU time 6.32 seconds
Started May 21 12:59:57 PM PDT 24
Finished May 21 01:00:04 PM PDT 24
Peak memory 226768 kb
Host smart-4e5b3971-a5c2-44ae-b65f-9bfc617e0e65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798825728 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.kmac_test_vectors_kmac.3798825728 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac_xof.2400461538
Short name T538
Test name
Test status
Simulation time 289625552 ps
CPU time 7.04 seconds
Started May 21 12:59:57 PM PDT 24
Finished May 21 01:00:05 PM PDT 24
Peak memory 226668 kb
Host smart-0fc597d0-c482-445f-8cd4-69720290d4b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400461538 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.kmac_test_vectors_kmac_xof.2400461538 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_224.4250363741
Short name T730
Test name
Test status
Simulation time 82126443319 ps
CPU time 2058.93 seconds
Started May 21 12:59:49 PM PDT 24
Finished May 21 01:34:09 PM PDT 24
Peak memory 400704 kb
Host smart-2575e341-a472-421e-a59b-b3ca06dc4c4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4250363741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_224.4250363741 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_256.1161390054
Short name T370
Test name
Test status
Simulation time 72108775373 ps
CPU time 2182.8 seconds
Started May 21 12:59:52 PM PDT 24
Finished May 21 01:36:15 PM PDT 24
Peak memory 401856 kb
Host smart-ac1aac6b-4c40-478d-ab3d-a113138740ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1161390054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_256.1161390054 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_384.2755431548
Short name T1036
Test name
Test status
Simulation time 187259887979 ps
CPU time 1757.68 seconds
Started May 21 12:59:55 PM PDT 24
Finished May 21 01:29:14 PM PDT 24
Peak memory 337636 kb
Host smart-1ca53931-ce71-4e57-9ae4-71453688bcbd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2755431548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_384.2755431548 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_512.4201879465
Short name T594
Test name
Test status
Simulation time 380283989125 ps
CPU time 1509.08 seconds
Started May 21 12:59:57 PM PDT 24
Finished May 21 01:25:07 PM PDT 24
Peak memory 301588 kb
Host smart-88de08bb-9a31-4f63-a2bd-0f01df423bb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4201879465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_512.4201879465 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_shake_128.2108200289
Short name T815
Test name
Test status
Simulation time 119728641479 ps
CPU time 4819.22 seconds
Started May 21 01:00:00 PM PDT 24
Finished May 21 02:20:21 PM PDT 24
Peak memory 647280 kb
Host smart-5de9f1b7-4f4e-44a7-824d-5f8289ca0e40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2108200289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_128.2108200289 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_shake_256.67765432
Short name T812
Test name
Test status
Simulation time 54397812498 ps
CPU time 4145.49 seconds
Started May 21 12:59:55 PM PDT 24
Finished May 21 02:09:02 PM PDT 24
Peak memory 567784 kb
Host smart-42a5e2f6-6fbd-4fa1-84d0-9e2229988c9a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=67765432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_256.67765432 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/47.kmac_alert_test.222872380
Short name T727
Test name
Test status
Simulation time 17624219 ps
CPU time 0.84 seconds
Started May 21 01:00:26 PM PDT 24
Finished May 21 01:00:27 PM PDT 24
Peak memory 218548 kb
Host smart-b1d415b2-e182-48d2-8eb8-fc8ee8abe1fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222872380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.222872380 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/47.kmac_alert_test/latest

Test location /workspace/coverage/default/47.kmac_app.3116475422
Short name T506
Test name
Test status
Simulation time 5854119691 ps
CPU time 387.07 seconds
Started May 21 01:00:19 PM PDT 24
Finished May 21 01:06:47 PM PDT 24
Peak memory 251540 kb
Host smart-83529868-597a-40d0-a9f4-d658686c0e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116475422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.3116475422 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_app/latest

Test location /workspace/coverage/default/47.kmac_burst_write.3918511288
Short name T91
Test name
Test status
Simulation time 22661836044 ps
CPU time 428.84 seconds
Started May 21 01:00:10 PM PDT 24
Finished May 21 01:07:20 PM PDT 24
Peak memory 238712 kb
Host smart-923739ed-c852-4836-aecb-779cd3eafef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918511288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.3918511288 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_burst_write/latest

Test location /workspace/coverage/default/47.kmac_entropy_refresh.2319051248
Short name T860
Test name
Test status
Simulation time 7600111227 ps
CPU time 177.3 seconds
Started May 21 01:00:20 PM PDT 24
Finished May 21 01:03:18 PM PDT 24
Peak memory 237400 kb
Host smart-c43f1d8b-244c-47a0-8864-b9b64c55c324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319051248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.2319051248 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/47.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/47.kmac_error.4146931894
Short name T813
Test name
Test status
Simulation time 1497947980 ps
CPU time 108.9 seconds
Started May 21 01:00:19 PM PDT 24
Finished May 21 01:02:09 PM PDT 24
Peak memory 243096 kb
Host smart-80befced-afb3-4727-ab25-4d29cec0ada0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146931894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.4146931894 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_error/latest

Test location /workspace/coverage/default/47.kmac_key_error.3438184829
Short name T631
Test name
Test status
Simulation time 6331385435 ps
CPU time 11.57 seconds
Started May 21 01:00:19 PM PDT 24
Finished May 21 01:00:32 PM PDT 24
Peak memory 218520 kb
Host smart-66bebf5d-358c-46a9-8fa7-4aa5bda4291f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438184829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.3438184829 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_key_error/latest

Test location /workspace/coverage/default/47.kmac_lc_escalation.1706099458
Short name T54
Test name
Test status
Simulation time 83558923 ps
CPU time 1.44 seconds
Started May 21 01:00:21 PM PDT 24
Finished May 21 01:00:23 PM PDT 24
Peak memory 218700 kb
Host smart-8f31fe44-f40d-4475-b27f-d699057ded55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706099458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.1706099458 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/47.kmac_lc_escalation/latest

Test location /workspace/coverage/default/47.kmac_long_msg_and_output.2698208270
Short name T123
Test name
Test status
Simulation time 6712475502 ps
CPU time 719.92 seconds
Started May 21 01:00:01 PM PDT 24
Finished May 21 01:12:01 PM PDT 24
Peak memory 285780 kb
Host smart-11a414b3-6465-4c41-96c1-a1de6e47257c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698208270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_a
nd_output.2698208270 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/47.kmac_sideload.2353279359
Short name T1047
Test name
Test status
Simulation time 15359320108 ps
CPU time 175.91 seconds
Started May 21 01:00:02 PM PDT 24
Finished May 21 01:02:59 PM PDT 24
Peak memory 235684 kb
Host smart-eb6e0266-0790-47ca-8def-94649747bd9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353279359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.2353279359 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_sideload/latest

Test location /workspace/coverage/default/47.kmac_smoke.3464003202
Short name T242
Test name
Test status
Simulation time 12052398833 ps
CPU time 21.37 seconds
Started May 21 01:00:01 PM PDT 24
Finished May 21 01:00:24 PM PDT 24
Peak memory 221608 kb
Host smart-652d282b-49b6-483d-911a-ffa0147eae4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464003202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.3464003202 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_smoke/latest

Test location /workspace/coverage/default/47.kmac_stress_all.1309923593
Short name T141
Test name
Test status
Simulation time 35990527103 ps
CPU time 928.2 seconds
Started May 21 01:00:22 PM PDT 24
Finished May 21 01:15:51 PM PDT 24
Peak memory 306660 kb
Host smart-680a02af-9d2c-4a33-a9dd-e24e3887eee4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1309923593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.1309923593 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_stress_all/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac.3247385656
Short name T298
Test name
Test status
Simulation time 921521972 ps
CPU time 6.17 seconds
Started May 21 01:00:14 PM PDT 24
Finished May 21 01:00:20 PM PDT 24
Peak memory 218604 kb
Host smart-173cf27e-7ef6-407e-ba25-bf225025dbbc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247385656 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.kmac_test_vectors_kmac.3247385656 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac_xof.3585160532
Short name T342
Test name
Test status
Simulation time 623053829 ps
CPU time 6.55 seconds
Started May 21 01:00:13 PM PDT 24
Finished May 21 01:00:20 PM PDT 24
Peak memory 226636 kb
Host smart-55df0156-049a-4d2e-b7f3-ad00543f00ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585160532 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.kmac_test_vectors_kmac_xof.3585160532 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_224.215797650
Short name T494
Test name
Test status
Simulation time 64959624377 ps
CPU time 2279.82 seconds
Started May 21 01:00:07 PM PDT 24
Finished May 21 01:38:08 PM PDT 24
Peak memory 393724 kb
Host smart-03c49876-b227-4508-8321-aee9e65bcdac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=215797650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_224.215797650 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_256.1855653008
Short name T425
Test name
Test status
Simulation time 438632494406 ps
CPU time 2354.23 seconds
Started May 21 01:00:07 PM PDT 24
Finished May 21 01:39:22 PM PDT 24
Peak memory 387872 kb
Host smart-2b7161a8-59a1-43fa-8f3e-c40f0e0f60ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1855653008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_256.1855653008 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_384.625901345
Short name T621
Test name
Test status
Simulation time 14788559713 ps
CPU time 1518.36 seconds
Started May 21 01:00:08 PM PDT 24
Finished May 21 01:25:27 PM PDT 24
Peak memory 337544 kb
Host smart-15aa9cb5-3c6e-4b5a-9fe3-565dfd0ddd12
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=625901345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_384.625901345 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_512.636385700
Short name T920
Test name
Test status
Simulation time 57840129480 ps
CPU time 1150.6 seconds
Started May 21 01:00:13 PM PDT 24
Finished May 21 01:19:24 PM PDT 24
Peak memory 297524 kb
Host smart-96aec7d6-920f-42e1-ae79-1f9435a61216
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=636385700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_512.636385700 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_shake_128.2769672173
Short name T198
Test name
Test status
Simulation time 915461311617 ps
CPU time 5512.65 seconds
Started May 21 01:00:14 PM PDT 24
Finished May 21 02:32:07 PM PDT 24
Peak memory 650748 kb
Host smart-90822f07-7dde-47e3-b0b4-3b744934d4ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2769672173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_128.2769672173 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_shake_256.3472258839
Short name T431
Test name
Test status
Simulation time 456929760935 ps
CPU time 5569.12 seconds
Started May 21 01:00:14 PM PDT 24
Finished May 21 02:33:04 PM PDT 24
Peak memory 572196 kb
Host smart-ab64a5df-bfd3-4dd5-ae38-b1462c5d9d71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3472258839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_256.3472258839 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/48.kmac_alert_test.1624120401
Short name T627
Test name
Test status
Simulation time 55529231 ps
CPU time 0.82 seconds
Started May 21 01:00:44 PM PDT 24
Finished May 21 01:00:46 PM PDT 24
Peak memory 218484 kb
Host smart-1a73352f-4462-42b0-8b87-4a65c007a1ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624120401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.1624120401 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_alert_test/latest

Test location /workspace/coverage/default/48.kmac_app.1826719386
Short name T443
Test name
Test status
Simulation time 161682075 ps
CPU time 4.58 seconds
Started May 21 01:00:38 PM PDT 24
Finished May 21 01:00:44 PM PDT 24
Peak memory 226640 kb
Host smart-e36b9c76-21f8-415e-80ab-0ef015c3dd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826719386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.1826719386 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_app/latest

Test location /workspace/coverage/default/48.kmac_burst_write.3186068509
Short name T853
Test name
Test status
Simulation time 69739393514 ps
CPU time 408.46 seconds
Started May 21 01:00:31 PM PDT 24
Finished May 21 01:07:20 PM PDT 24
Peak memory 231732 kb
Host smart-f5801934-3808-4e8e-a6c0-529a5b374fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186068509 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.3186068509 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_burst_write/latest

Test location /workspace/coverage/default/48.kmac_entropy_refresh.3356526363
Short name T735
Test name
Test status
Simulation time 1200566391 ps
CPU time 56.03 seconds
Started May 21 01:00:43 PM PDT 24
Finished May 21 01:01:39 PM PDT 24
Peak memory 229284 kb
Host smart-498d6e8d-bd76-43e9-81b4-b77e7c0390b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356526363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.3356526363 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/48.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/48.kmac_error.3489621297
Short name T524
Test name
Test status
Simulation time 820117825 ps
CPU time 58.26 seconds
Started May 21 01:00:43 PM PDT 24
Finished May 21 01:01:42 PM PDT 24
Peak memory 243112 kb
Host smart-2a474dbb-f1a6-494d-9203-10c2304581c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489621297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.3489621297 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_error/latest

Test location /workspace/coverage/default/48.kmac_key_error.3692590118
Short name T434
Test name
Test status
Simulation time 477447571 ps
CPU time 2.27 seconds
Started May 21 01:00:43 PM PDT 24
Finished May 21 01:00:45 PM PDT 24
Peak memory 218680 kb
Host smart-fdd0ce5b-24cd-49c9-9457-edaf42a81995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692590118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.3692590118 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_key_error/latest

Test location /workspace/coverage/default/48.kmac_lc_escalation.2100436653
Short name T144
Test name
Test status
Simulation time 520745187 ps
CPU time 12.54 seconds
Started May 21 01:00:45 PM PDT 24
Finished May 21 01:00:59 PM PDT 24
Peak memory 231300 kb
Host smart-442ce12a-b989-4b7f-a1e7-14f227cad0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100436653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.2100436653 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/48.kmac_lc_escalation/latest

Test location /workspace/coverage/default/48.kmac_long_msg_and_output.2129131224
Short name T1057
Test name
Test status
Simulation time 118926959150 ps
CPU time 2843.64 seconds
Started May 21 01:00:26 PM PDT 24
Finished May 21 01:47:51 PM PDT 24
Peak memory 473376 kb
Host smart-68a366fe-71ef-4b0a-9f1e-90fde8c819f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129131224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_a
nd_output.2129131224 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/48.kmac_sideload.3104234489
Short name T933
Test name
Test status
Simulation time 70937386796 ps
CPU time 310.12 seconds
Started May 21 01:00:31 PM PDT 24
Finished May 21 01:05:42 PM PDT 24
Peak memory 242868 kb
Host smart-cd93232b-262a-43ec-ba6c-9386ae2f5c26
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104234489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.3104234489 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_sideload/latest

Test location /workspace/coverage/default/48.kmac_smoke.4054926536
Short name T1002
Test name
Test status
Simulation time 518871813 ps
CPU time 5.68 seconds
Started May 21 01:00:24 PM PDT 24
Finished May 21 01:00:31 PM PDT 24
Peak memory 226680 kb
Host smart-1c18453c-c503-469f-8dfe-9f591212fd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054926536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.4054926536 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_smoke/latest

Test location /workspace/coverage/default/48.kmac_stress_all.4053062751
Short name T640
Test name
Test status
Simulation time 20320709083 ps
CPU time 176.98 seconds
Started May 21 01:00:56 PM PDT 24
Finished May 21 01:03:54 PM PDT 24
Peak memory 254812 kb
Host smart-3e3ffef2-4445-4016-8091-5cb3c651a2fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4053062751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.4053062751 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_stress_all/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac.4249479315
Short name T816
Test name
Test status
Simulation time 213063078 ps
CPU time 6.08 seconds
Started May 21 01:00:37 PM PDT 24
Finished May 21 01:00:44 PM PDT 24
Peak memory 218620 kb
Host smart-078dd7f2-93d1-4338-b7af-1402f04355b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249479315 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.kmac_test_vectors_kmac.4249479315 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac_xof.3666379221
Short name T481
Test name
Test status
Simulation time 406794760 ps
CPU time 6.71 seconds
Started May 21 01:00:37 PM PDT 24
Finished May 21 01:00:45 PM PDT 24
Peak memory 226596 kb
Host smart-525917b3-387a-4ade-8fc9-86a83d95541d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666379221 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.kmac_test_vectors_kmac_xof.3666379221 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_224.2984602520
Short name T552
Test name
Test status
Simulation time 135390016069 ps
CPU time 2256.55 seconds
Started May 21 01:00:30 PM PDT 24
Finished May 21 01:38:07 PM PDT 24
Peak memory 408080 kb
Host smart-3d9f0134-0ad3-4597-b824-7e3a5ea6e9eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2984602520 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_224.2984602520 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_256.2760457918
Short name T693
Test name
Test status
Simulation time 126584653448 ps
CPU time 2058.67 seconds
Started May 21 01:00:31 PM PDT 24
Finished May 21 01:34:51 PM PDT 24
Peak memory 365200 kb
Host smart-d38a488e-be2f-4731-a6ae-2eb6c8e0ffdc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2760457918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_256.2760457918 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_384.896294257
Short name T412
Test name
Test status
Simulation time 63544316003 ps
CPU time 1594.7 seconds
Started May 21 01:00:41 PM PDT 24
Finished May 21 01:27:16 PM PDT 24
Peak memory 344032 kb
Host smart-9e12dc81-31a3-4d1f-a77a-7cde03226adf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=896294257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_384.896294257 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_512.3981396070
Short name T695
Test name
Test status
Simulation time 10887753855 ps
CPU time 1132.48 seconds
Started May 21 01:00:37 PM PDT 24
Finished May 21 01:19:31 PM PDT 24
Peak memory 294204 kb
Host smart-754e0ddf-1370-4c4a-91a4-fbe7f3e9af47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3981396070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_512.3981396070 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_shake_128.4423214
Short name T182
Test name
Test status
Simulation time 60184523578 ps
CPU time 5312.19 seconds
Started May 21 01:00:37 PM PDT 24
Finished May 21 02:29:11 PM PDT 24
Peak memory 661396 kb
Host smart-d7aaf490-71c5-4ec8-88a4-c45912ef11f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4423214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_128.4423214 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_shake_256.3909252648
Short name T973
Test name
Test status
Simulation time 232990961387 ps
CPU time 5039.33 seconds
Started May 21 01:00:37 PM PDT 24
Finished May 21 02:24:38 PM PDT 24
Peak memory 579328 kb
Host smart-9c553cf4-c829-4fff-90cf-906f9d2c1789
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3909252648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_256.3909252648 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/49.kmac_alert_test.540832126
Short name T386
Test name
Test status
Simulation time 124662714 ps
CPU time 0.86 seconds
Started May 21 01:01:07 PM PDT 24
Finished May 21 01:01:08 PM PDT 24
Peak memory 218448 kb
Host smart-c604c346-6678-43d5-acc8-936ebc6eab58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540832126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.540832126 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/49.kmac_alert_test/latest

Test location /workspace/coverage/default/49.kmac_app.4082483579
Short name T289
Test name
Test status
Simulation time 2896475426 ps
CPU time 77.73 seconds
Started May 21 01:01:00 PM PDT 24
Finished May 21 01:02:19 PM PDT 24
Peak memory 230996 kb
Host smart-a5e2d6e3-ea68-43cc-82a4-193748aa140c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082483579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.4082483579 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_app/latest

Test location /workspace/coverage/default/49.kmac_burst_write.3361804843
Short name T916
Test name
Test status
Simulation time 56053300900 ps
CPU time 1471.52 seconds
Started May 21 01:00:48 PM PDT 24
Finished May 21 01:25:20 PM PDT 24
Peak memory 238020 kb
Host smart-5a73cdf0-a3bc-4a3a-aede-6489e1f440d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361804843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.3361804843 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_burst_write/latest

Test location /workspace/coverage/default/49.kmac_entropy_refresh.3122341562
Short name T872
Test name
Test status
Simulation time 41596531348 ps
CPU time 260.71 seconds
Started May 21 01:01:00 PM PDT 24
Finished May 21 01:05:21 PM PDT 24
Peak memory 246680 kb
Host smart-2073d5c6-8893-462c-82de-044b3623aa34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122341562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.3122341562 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/49.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/49.kmac_error.971319136
Short name T1013
Test name
Test status
Simulation time 21255157177 ps
CPU time 147.28 seconds
Started May 21 01:01:00 PM PDT 24
Finished May 21 01:03:27 PM PDT 24
Peak memory 251332 kb
Host smart-6f68c59d-870e-4f0b-8af9-01ea6c5d675c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971319136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.971319136 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_error/latest

Test location /workspace/coverage/default/49.kmac_key_error.256283265
Short name T574
Test name
Test status
Simulation time 7169669261 ps
CPU time 12.76 seconds
Started May 21 01:01:06 PM PDT 24
Finished May 21 01:01:20 PM PDT 24
Peak memory 218536 kb
Host smart-971cfed1-66ea-4d6f-910f-9a4bc2fe0747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256283265 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.256283265 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_key_error/latest

Test location /workspace/coverage/default/49.kmac_lc_escalation.515416454
Short name T507
Test name
Test status
Simulation time 62959755 ps
CPU time 1.3 seconds
Started May 21 01:01:06 PM PDT 24
Finished May 21 01:01:08 PM PDT 24
Peak memory 218708 kb
Host smart-f9b10aaf-4d30-4725-ad45-ef168d8d853b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515416454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.515416454 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/49.kmac_lc_escalation/latest

Test location /workspace/coverage/default/49.kmac_long_msg_and_output.4137896706
Short name T936
Test name
Test status
Simulation time 164587807750 ps
CPU time 1610.33 seconds
Started May 21 01:00:44 PM PDT 24
Finished May 21 01:27:35 PM PDT 24
Peak memory 352616 kb
Host smart-430bb906-fcea-4e84-86bd-a84c0903feff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137896706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_a
nd_output.4137896706 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/49.kmac_sideload.3681269099
Short name T405
Test name
Test status
Simulation time 9666450547 ps
CPU time 315.02 seconds
Started May 21 01:00:51 PM PDT 24
Finished May 21 01:06:06 PM PDT 24
Peak memory 246012 kb
Host smart-2092df0b-1e0c-44fe-bd6d-ff4851595dc7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681269099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.3681269099 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_sideload/latest

Test location /workspace/coverage/default/49.kmac_smoke.334751457
Short name T473
Test name
Test status
Simulation time 7465689811 ps
CPU time 58.41 seconds
Started May 21 01:00:44 PM PDT 24
Finished May 21 01:01:44 PM PDT 24
Peak memory 223416 kb
Host smart-3b6c9b1b-6d42-4068-b223-74ee74394e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334751457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.334751457 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_smoke/latest

Test location /workspace/coverage/default/49.kmac_stress_all.1276851163
Short name T426
Test name
Test status
Simulation time 3145044399 ps
CPU time 167.03 seconds
Started May 21 01:01:07 PM PDT 24
Finished May 21 01:03:54 PM PDT 24
Peak memory 251608 kb
Host smart-9ae4e587-ecf5-43a2-b1d0-6167c5e55ed5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1276851163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.1276851163 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_stress_all/latest

Test location /workspace/coverage/default/49.kmac_stress_all_with_rand_reset.2524710314
Short name T25
Test name
Test status
Simulation time 12727270893 ps
CPU time 164.22 seconds
Started May 21 01:01:08 PM PDT 24
Finished May 21 01:03:52 PM PDT 24
Peak memory 251484 kb
Host smart-6ab7ce25-7b55-48b1-a4f0-77536fde00cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2524710314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all_with_rand_reset.2524710314 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac.4289953161
Short name T788
Test name
Test status
Simulation time 185488496 ps
CPU time 6.71 seconds
Started May 21 01:00:54 PM PDT 24
Finished May 21 01:01:01 PM PDT 24
Peak memory 218676 kb
Host smart-ff942d2c-89d1-432b-8767-720afc719af2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289953161 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.kmac_test_vectors_kmac.4289953161 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac_xof.3526958049
Short name T222
Test name
Test status
Simulation time 1277487598 ps
CPU time 7.33 seconds
Started May 21 01:01:00 PM PDT 24
Finished May 21 01:01:08 PM PDT 24
Peak memory 218564 kb
Host smart-7d85ebe0-24a8-4816-a7db-cffc481c6199
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526958049 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.kmac_test_vectors_kmac_xof.3526958049 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_224.2622836974
Short name T307
Test name
Test status
Simulation time 654586035785 ps
CPU time 2502.56 seconds
Started May 21 01:00:49 PM PDT 24
Finished May 21 01:42:32 PM PDT 24
Peak memory 397188 kb
Host smart-d79a8cce-b72f-4258-be68-be8a2af52957
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2622836974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_224.2622836974 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_256.825940815
Short name T103
Test name
Test status
Simulation time 61191440415 ps
CPU time 2062.41 seconds
Started May 21 01:00:55 PM PDT 24
Finished May 21 01:35:18 PM PDT 24
Peak memory 380652 kb
Host smart-1fc7a1e5-7abf-4b1b-91ec-d141a0899e59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=825940815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_256.825940815 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_384.1060278602
Short name T978
Test name
Test status
Simulation time 51328431746 ps
CPU time 1729.75 seconds
Started May 21 01:00:54 PM PDT 24
Finished May 21 01:29:45 PM PDT 24
Peak memory 350820 kb
Host smart-f7e9dd87-ef66-4bef-bf54-be7d203f33c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1060278602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_384.1060278602 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_512.678603467
Short name T466
Test name
Test status
Simulation time 132533292908 ps
CPU time 1222.4 seconds
Started May 21 01:00:56 PM PDT 24
Finished May 21 01:21:20 PM PDT 24
Peak memory 299920 kb
Host smart-9d2386d3-172c-405f-9f27-e5ed7b226970
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=678603467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_512.678603467 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_shake_128.2250585870
Short name T657
Test name
Test status
Simulation time 62381020787 ps
CPU time 5133.39 seconds
Started May 21 01:00:54 PM PDT 24
Finished May 21 02:26:29 PM PDT 24
Peak memory 657132 kb
Host smart-9926c125-bc8a-4494-bb33-3ef3c1ab92bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2250585870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_128.2250585870 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_shake_256.3317198444
Short name T504
Test name
Test status
Simulation time 464222877950 ps
CPU time 4802.84 seconds
Started May 21 01:00:54 PM PDT 24
Finished May 21 02:20:58 PM PDT 24
Peak memory 565584 kb
Host smart-299a55f1-b60a-4512-843a-9cc39e10af5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3317198444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_256.3317198444 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/5.kmac_alert_test.682518051
Short name T633
Test name
Test status
Simulation time 93676045 ps
CPU time 0.87 seconds
Started May 21 12:53:35 PM PDT 24
Finished May 21 12:53:38 PM PDT 24
Peak memory 218444 kb
Host smart-49042885-fe4c-4b08-b404-08b2b010c81b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682518051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.682518051 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/5.kmac_alert_test/latest

Test location /workspace/coverage/default/5.kmac_app.1453479772
Short name T562
Test name
Test status
Simulation time 14202707659 ps
CPU time 203.37 seconds
Started May 21 12:53:29 PM PDT 24
Finished May 21 12:56:56 PM PDT 24
Peak memory 241792 kb
Host smart-51b485dd-77fd-4122-9a37-eb9aba496a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453479772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.1453479772 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_app/latest

Test location /workspace/coverage/default/5.kmac_app_with_partial_data.2201408038
Short name T904
Test name
Test status
Simulation time 78569725303 ps
CPU time 338.2 seconds
Started May 21 12:53:40 PM PDT 24
Finished May 21 12:59:19 PM PDT 24
Peak memory 251452 kb
Host smart-71356711-cd19-4100-93f6-02a7d5be2660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201408038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.2201408038 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/5.kmac_burst_write.3758014412
Short name T705
Test name
Test status
Simulation time 11422545315 ps
CPU time 948.73 seconds
Started May 21 12:53:33 PM PDT 24
Finished May 21 01:09:25 PM PDT 24
Peak memory 236272 kb
Host smart-ab84da37-4cb0-49b8-9e45-04c9f798642b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758014412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.3758014412 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_burst_write/latest

Test location /workspace/coverage/default/5.kmac_edn_timeout_error.1044908060
Short name T577
Test name
Test status
Simulation time 87635968 ps
CPU time 1.15 seconds
Started May 21 12:53:44 PM PDT 24
Finished May 21 12:53:49 PM PDT 24
Peak memory 218500 kb
Host smart-f98ab054-5fe0-4d53-8aa6-0057e1e8cc65
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1044908060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.1044908060 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_mode_error.1333574546
Short name T408
Test name
Test status
Simulation time 36881876 ps
CPU time 0.88 seconds
Started May 21 12:53:42 PM PDT 24
Finished May 21 12:53:45 PM PDT 24
Peak memory 220364 kb
Host smart-acef507d-e6f2-4b0f-9ae9-a7010f7b2f6e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1333574546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.1333574546 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_ready_error.2191902419
Short name T715
Test name
Test status
Simulation time 3029288894 ps
CPU time 40.02 seconds
Started May 21 12:53:34 PM PDT 24
Finished May 21 12:54:17 PM PDT 24
Peak memory 226688 kb
Host smart-b02ffe3a-7ab7-432a-a185-1b615a700749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191902419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.2191902419 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_refresh.2865369213
Short name T255
Test name
Test status
Simulation time 28642357002 ps
CPU time 214.29 seconds
Started May 21 12:53:34 PM PDT 24
Finished May 21 12:57:11 PM PDT 24
Peak memory 242888 kb
Host smart-6be0a1e0-7d0c-4c31-8279-0a5470a273a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865369213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.2865369213 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/5.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/5.kmac_key_error.4136029750
Short name T1027
Test name
Test status
Simulation time 1945246889 ps
CPU time 13.31 seconds
Started May 21 12:53:33 PM PDT 24
Finished May 21 12:53:50 PM PDT 24
Peak memory 218456 kb
Host smart-2b98c0c8-bbc0-41fd-91a9-8adc7dd27646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136029750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.4136029750 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_key_error/latest

Test location /workspace/coverage/default/5.kmac_long_msg_and_output.1624871236
Short name T912
Test name
Test status
Simulation time 43005857207 ps
CPU time 1123.2 seconds
Started May 21 12:53:59 PM PDT 24
Finished May 21 01:12:45 PM PDT 24
Peak memory 315324 kb
Host smart-ba4865db-bcd4-4c42-9c9f-e599512606c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624871236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_an
d_output.1624871236 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/5.kmac_mubi.1249901429
Short name T61
Test name
Test status
Simulation time 21910163228 ps
CPU time 34.71 seconds
Started May 21 12:53:33 PM PDT 24
Finished May 21 12:54:11 PM PDT 24
Peak memory 227860 kb
Host smart-8c50ddb3-122a-4d87-9235-ef0c32d6d077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249901429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.1249901429 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_mubi/latest

Test location /workspace/coverage/default/5.kmac_sideload.1206767381
Short name T696
Test name
Test status
Simulation time 21874586014 ps
CPU time 463.74 seconds
Started May 21 12:53:50 PM PDT 24
Finished May 21 01:01:38 PM PDT 24
Peak memory 254472 kb
Host smart-df507afa-8bff-4130-8c2b-14205598abf5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206767381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.1206767381 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_sideload/latest

Test location /workspace/coverage/default/5.kmac_smoke.2373115734
Short name T357
Test name
Test status
Simulation time 3764083994 ps
CPU time 28.55 seconds
Started May 21 12:53:30 PM PDT 24
Finished May 21 12:54:02 PM PDT 24
Peak memory 226680 kb
Host smart-e50af5f3-a596-48af-9b89-792a97c83a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373115734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.2373115734 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_smoke/latest

Test location /workspace/coverage/default/5.kmac_stress_all_with_rand_reset.3425089858
Short name T45
Test name
Test status
Simulation time 53919357151 ps
CPU time 483.89 seconds
Started May 21 12:53:33 PM PDT 24
Finished May 21 01:01:40 PM PDT 24
Peak memory 275300 kb
Host smart-1b0ac6b1-e77c-45e6-910d-e29e8f6ed803
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3425089858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all_with_rand_reset.3425089858 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac.2681058904
Short name T33
Test name
Test status
Simulation time 295954329 ps
CPU time 6.28 seconds
Started May 21 12:53:29 PM PDT 24
Finished May 21 12:53:38 PM PDT 24
Peak memory 218644 kb
Host smart-8c77ca90-9b22-4edf-93c9-16ba8d4754ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681058904 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.kmac_test_vectors_kmac.2681058904 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac_xof.638736588
Short name T924
Test name
Test status
Simulation time 348425816 ps
CPU time 5.56 seconds
Started May 21 12:53:51 PM PDT 24
Finished May 21 12:54:01 PM PDT 24
Peak memory 218612 kb
Host smart-d2fc6456-e818-499f-a51b-ca91a73164ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638736588 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.kmac_test_vectors_kmac_xof.638736588 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_224.2036590641
Short name T435
Test name
Test status
Simulation time 20477917479 ps
CPU time 1772.27 seconds
Started May 21 12:53:46 PM PDT 24
Finished May 21 01:23:22 PM PDT 24
Peak memory 394268 kb
Host smart-051ec381-77b4-4040-ab31-731f568b7fc8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2036590641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_224.2036590641 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_256.3019109239
Short name T261
Test name
Test status
Simulation time 1325475291026 ps
CPU time 2386.89 seconds
Started May 21 12:53:46 PM PDT 24
Finished May 21 01:33:37 PM PDT 24
Peak memory 386664 kb
Host smart-af395a71-7ed0-4253-9049-cd472462ae09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3019109239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_256.3019109239 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_384.1732494629
Short name T737
Test name
Test status
Simulation time 49482685718 ps
CPU time 1771.73 seconds
Started May 21 12:53:33 PM PDT 24
Finished May 21 01:23:08 PM PDT 24
Peak memory 342608 kb
Host smart-bc06609e-236b-4d96-8e8f-7237d82b05a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1732494629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_384.1732494629 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_512.1678117571
Short name T397
Test name
Test status
Simulation time 63665434993 ps
CPU time 1266.48 seconds
Started May 21 12:53:28 PM PDT 24
Finished May 21 01:14:38 PM PDT 24
Peak memory 298584 kb
Host smart-c5702885-1ac4-4a08-80ef-89133535c5ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1678117571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_512.1678117571 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_shake_128.1335876091
Short name T214
Test name
Test status
Simulation time 129004081733 ps
CPU time 5206.48 seconds
Started May 21 12:53:40 PM PDT 24
Finished May 21 02:20:29 PM PDT 24
Peak memory 671480 kb
Host smart-c21be284-3fe5-4838-95d3-464b7eb51e6c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1335876091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_128.1335876091 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_shake_256.322330383
Short name T1044
Test name
Test status
Simulation time 686337507973 ps
CPU time 5009.95 seconds
Started May 21 12:53:30 PM PDT 24
Finished May 21 02:17:04 PM PDT 24
Peak memory 561120 kb
Host smart-1f5bd8e5-7fd2-4237-9fb7-f258cfa701e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=322330383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_256.322330383 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/6.kmac_alert_test.2093098190
Short name T697
Test name
Test status
Simulation time 15288067 ps
CPU time 0.76 seconds
Started May 21 12:53:37 PM PDT 24
Finished May 21 12:53:40 PM PDT 24
Peak memory 218524 kb
Host smart-c36d6c84-dcc9-434d-8fc2-4da7229aa0e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093098190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.2093098190 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_alert_test/latest

Test location /workspace/coverage/default/6.kmac_app.4275699830
Short name T499
Test name
Test status
Simulation time 5734265625 ps
CPU time 139.98 seconds
Started May 21 12:53:36 PM PDT 24
Finished May 21 12:55:59 PM PDT 24
Peak memory 236348 kb
Host smart-ee0ccfd1-16d7-41b5-80f6-803c883ad450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275699830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.4275699830 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_app/latest

Test location /workspace/coverage/default/6.kmac_app_with_partial_data.3151865115
Short name T795
Test name
Test status
Simulation time 50467814640 ps
CPU time 243.71 seconds
Started May 21 12:53:57 PM PDT 24
Finished May 21 12:58:04 PM PDT 24
Peak memory 244412 kb
Host smart-64d48592-042e-4668-9285-a65841454b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151865115 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.3151865115 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/6.kmac_burst_write.1646763261
Short name T1038
Test name
Test status
Simulation time 35375190416 ps
CPU time 1405.44 seconds
Started May 21 12:53:33 PM PDT 24
Finished May 21 01:17:02 PM PDT 24
Peak memory 238604 kb
Host smart-f24d4dc7-a008-4878-b106-35117c0015d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646763261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.1646763261 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_burst_write/latest

Test location /workspace/coverage/default/6.kmac_entropy_mode_error.3425476024
Short name T246
Test name
Test status
Simulation time 22889679 ps
CPU time 0.96 seconds
Started May 21 12:53:37 PM PDT 24
Finished May 21 12:53:40 PM PDT 24
Peak memory 220456 kb
Host smart-4dfa401d-c45a-44b2-94ab-c59d7657f3b8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3425476024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.3425476024 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_ready_error.2132594030
Short name T692
Test name
Test status
Simulation time 9309784957 ps
CPU time 65.69 seconds
Started May 21 12:53:45 PM PDT 24
Finished May 21 12:54:54 PM PDT 24
Peak memory 226768 kb
Host smart-cfcc301e-1ec6-48f7-8fef-b859a60e0386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132594030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.2132594030 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_refresh.3006519130
Short name T606
Test name
Test status
Simulation time 29206943048 ps
CPU time 168.75 seconds
Started May 21 12:53:37 PM PDT 24
Finished May 21 12:56:28 PM PDT 24
Peak memory 243148 kb
Host smart-1da6f2ac-4889-4d86-a6f9-77eb732845f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006519130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.3006519130 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/6.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/6.kmac_error.1820899860
Short name T984
Test name
Test status
Simulation time 11138231000 ps
CPU time 298.15 seconds
Started May 21 12:53:44 PM PDT 24
Finished May 21 12:58:45 PM PDT 24
Peak memory 257236 kb
Host smart-b83e2fe0-821d-4af7-91d3-56443480d454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820899860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.1820899860 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_error/latest

Test location /workspace/coverage/default/6.kmac_key_error.2208508421
Short name T967
Test name
Test status
Simulation time 3705676314 ps
CPU time 6.52 seconds
Started May 21 12:53:54 PM PDT 24
Finished May 21 12:54:04 PM PDT 24
Peak memory 218600 kb
Host smart-4f68e1e7-708e-4270-baf9-f39e4fb54216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208508421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.2208508421 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_key_error/latest

Test location /workspace/coverage/default/6.kmac_lc_escalation.1020721013
Short name T525
Test name
Test status
Simulation time 1577393504 ps
CPU time 28.77 seconds
Started May 21 12:53:33 PM PDT 24
Finished May 21 12:54:05 PM PDT 24
Peak memory 234992 kb
Host smart-24310778-017e-49de-b8f5-1fe4da7aab59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020721013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.1020721013 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/6.kmac_lc_escalation/latest

Test location /workspace/coverage/default/6.kmac_long_msg_and_output.736597005
Short name T379
Test name
Test status
Simulation time 540796661572 ps
CPU time 1976.95 seconds
Started May 21 12:53:47 PM PDT 24
Finished May 21 01:26:48 PM PDT 24
Peak memory 375288 kb
Host smart-80e34820-8c3f-4578-b132-f5da290b4eeb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736597005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_and
_output.736597005 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/6.kmac_mubi.3955875627
Short name T40
Test name
Test status
Simulation time 20998348216 ps
CPU time 352.2 seconds
Started May 21 12:53:49 PM PDT 24
Finished May 21 12:59:45 PM PDT 24
Peak memory 250552 kb
Host smart-44e8d98c-c315-49cc-9f26-37c209fef35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955875627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.3955875627 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_mubi/latest

Test location /workspace/coverage/default/6.kmac_sideload.2888838554
Short name T864
Test name
Test status
Simulation time 9256590374 ps
CPU time 131.84 seconds
Started May 21 12:53:39 PM PDT 24
Finished May 21 12:55:53 PM PDT 24
Peak memory 235780 kb
Host smart-0657d49d-4068-4ba7-94ff-86318fdd7900
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888838554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.2888838554 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_sideload/latest

Test location /workspace/coverage/default/6.kmac_smoke.4194350922
Short name T247
Test name
Test status
Simulation time 7554042014 ps
CPU time 38.57 seconds
Started May 21 12:53:46 PM PDT 24
Finished May 21 12:54:28 PM PDT 24
Peak memory 226668 kb
Host smart-25468b65-788e-4386-bed2-60f64cf3c339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194350922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.4194350922 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_smoke/latest

Test location /workspace/coverage/default/6.kmac_stress_all.111965877
Short name T604
Test name
Test status
Simulation time 335370970891 ps
CPU time 1560.77 seconds
Started May 21 12:53:47 PM PDT 24
Finished May 21 01:19:52 PM PDT 24
Peak memory 357960 kb
Host smart-8646f52b-00df-4767-9718-485da16266f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=111965877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.111965877 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_stress_all/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac.1708349806
Short name T277
Test name
Test status
Simulation time 419417292 ps
CPU time 6.23 seconds
Started May 21 12:53:36 PM PDT 24
Finished May 21 12:53:44 PM PDT 24
Peak memory 219540 kb
Host smart-eaf4bd68-b273-4234-b389-2fc403bcebe6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708349806 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.kmac_test_vectors_kmac.1708349806 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac_xof.4222784941
Short name T811
Test name
Test status
Simulation time 848362095 ps
CPU time 5.6 seconds
Started May 21 12:54:04 PM PDT 24
Finished May 21 12:54:13 PM PDT 24
Peak memory 218516 kb
Host smart-a3855d49-036b-4c4c-89f7-07c7c5ea2cbd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222784941 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.kmac_test_vectors_kmac_xof.4222784941 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_224.2920934638
Short name T297
Test name
Test status
Simulation time 78387982228 ps
CPU time 2103.2 seconds
Started May 21 12:53:49 PM PDT 24
Finished May 21 01:28:56 PM PDT 24
Peak memory 397932 kb
Host smart-ad743903-e5c0-4203-8877-0b8bb554a4df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2920934638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_224.2920934638 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_256.3610976104
Short name T1001
Test name
Test status
Simulation time 127529109007 ps
CPU time 2130.06 seconds
Started May 21 12:53:52 PM PDT 24
Finished May 21 01:29:26 PM PDT 24
Peak memory 387708 kb
Host smart-b12698fe-729d-4682-9a4b-d1f295a406dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3610976104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_256.3610976104 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_384.2500057944
Short name T1055
Test name
Test status
Simulation time 77283361369 ps
CPU time 1738.07 seconds
Started May 21 12:53:52 PM PDT 24
Finished May 21 01:22:55 PM PDT 24
Peak memory 345624 kb
Host smart-455d549b-9e5c-490b-b525-f64f655adccd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2500057944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_384.2500057944 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_512.3514826860
Short name T306
Test name
Test status
Simulation time 43368646895 ps
CPU time 1063.96 seconds
Started May 21 12:53:54 PM PDT 24
Finished May 21 01:11:43 PM PDT 24
Peak memory 300920 kb
Host smart-64c7f757-4ac4-4c08-8834-e4dee86be47a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3514826860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_512.3514826860 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_128.1236042027
Short name T488
Test name
Test status
Simulation time 72721643237 ps
CPU time 5097.4 seconds
Started May 21 12:53:52 PM PDT 24
Finished May 21 02:18:54 PM PDT 24
Peak memory 652164 kb
Host smart-bd101aeb-0d28-4d67-a73f-a806af350946
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1236042027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_128.1236042027 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_256.1090608688
Short name T1004
Test name
Test status
Simulation time 194199266336 ps
CPU time 4705.32 seconds
Started May 21 12:53:38 PM PDT 24
Finished May 21 02:12:06 PM PDT 24
Peak memory 561468 kb
Host smart-b7e573fa-a8d1-4f43-9b1b-f7b2172a3eba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1090608688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_256.1090608688 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/7.kmac_alert_test.2825629592
Short name T672
Test name
Test status
Simulation time 49175479 ps
CPU time 0.85 seconds
Started May 21 12:53:35 PM PDT 24
Finished May 21 12:53:39 PM PDT 24
Peak memory 218552 kb
Host smart-352a12e4-8244-48a2-91a7-90fea79c52ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825629592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.2825629592 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_alert_test/latest

Test location /workspace/coverage/default/7.kmac_app.3826555854
Short name T284
Test name
Test status
Simulation time 30852788057 ps
CPU time 370.75 seconds
Started May 21 12:53:34 PM PDT 24
Finished May 21 12:59:48 PM PDT 24
Peak memory 252332 kb
Host smart-519a6d83-2991-4763-91b3-e227d454abd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826555854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.3826555854 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_app/latest

Test location /workspace/coverage/default/7.kmac_app_with_partial_data.367834824
Short name T419
Test name
Test status
Simulation time 52885969097 ps
CPU time 304.21 seconds
Started May 21 12:53:34 PM PDT 24
Finished May 21 12:58:41 PM PDT 24
Peak memory 248356 kb
Host smart-af89c978-bbca-409f-bb83-ab492c945c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367834824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.367834824 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/7.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/7.kmac_burst_write.737069263
Short name T881
Test name
Test status
Simulation time 6604750058 ps
CPU time 680.1 seconds
Started May 21 12:53:45 PM PDT 24
Finished May 21 01:05:09 PM PDT 24
Peak memory 234600 kb
Host smart-1ec404d0-380e-4295-96ac-859e06c70e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737069263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.737069263 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_burst_write/latest

Test location /workspace/coverage/default/7.kmac_edn_timeout_error.1154990291
Short name T244
Test name
Test status
Simulation time 12674300575 ps
CPU time 45.58 seconds
Started May 21 12:54:06 PM PDT 24
Finished May 21 12:54:55 PM PDT 24
Peak memory 243052 kb
Host smart-e6c6b27d-c03d-47ce-8ae0-af1638d8e646
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1154990291 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.1154990291 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_mode_error.3585200979
Short name T1031
Test name
Test status
Simulation time 32826102 ps
CPU time 1.02 seconds
Started May 21 12:53:49 PM PDT 24
Finished May 21 12:53:53 PM PDT 24
Peak memory 220468 kb
Host smart-294db795-d4f2-43ca-bd18-dee0316768ec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3585200979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.3585200979 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_ready_error.3361179832
Short name T655
Test name
Test status
Simulation time 13627403700 ps
CPU time 34.64 seconds
Started May 21 12:54:01 PM PDT 24
Finished May 21 12:54:39 PM PDT 24
Peak memory 226788 kb
Host smart-a2c4a69f-444d-4d56-8965-799177563e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361179832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.3361179832 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/7.kmac_error.2008653730
Short name T580
Test name
Test status
Simulation time 2072864011 ps
CPU time 32.79 seconds
Started May 21 12:53:50 PM PDT 24
Finished May 21 12:54:27 PM PDT 24
Peak memory 242500 kb
Host smart-66cb45ea-7efd-405f-8a84-41e8abcf14fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008653730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.2008653730 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_error/latest

Test location /workspace/coverage/default/7.kmac_key_error.3292935699
Short name T752
Test name
Test status
Simulation time 1395485596 ps
CPU time 8.41 seconds
Started May 21 12:53:34 PM PDT 24
Finished May 21 12:53:45 PM PDT 24
Peak memory 218488 kb
Host smart-9f005941-4197-4735-801f-7b3187c9f803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292935699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.3292935699 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_key_error/latest

Test location /workspace/coverage/default/7.kmac_lc_escalation.249932828
Short name T50
Test name
Test status
Simulation time 50584541 ps
CPU time 1.44 seconds
Started May 21 12:53:33 PM PDT 24
Finished May 21 12:53:37 PM PDT 24
Peak memory 218652 kb
Host smart-970e61fb-40d4-471a-8299-42aab5f83987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249932828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.249932828 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_lc_escalation/latest

Test location /workspace/coverage/default/7.kmac_long_msg_and_output.1610202587
Short name T566
Test name
Test status
Simulation time 9282187204 ps
CPU time 448.08 seconds
Started May 21 12:53:51 PM PDT 24
Finished May 21 01:01:24 PM PDT 24
Peak memory 264864 kb
Host smart-cea70864-21c1-4ba6-a1a1-24085801d20b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610202587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_an
d_output.1610202587 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/7.kmac_mubi.2406731606
Short name T996
Test name
Test status
Simulation time 100098962274 ps
CPU time 413.74 seconds
Started May 21 12:53:37 PM PDT 24
Finished May 21 01:00:33 PM PDT 24
Peak memory 251796 kb
Host smart-812cac70-fadf-4984-a55b-5f75326de22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406731606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.2406731606 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_mubi/latest

Test location /workspace/coverage/default/7.kmac_sideload.1769735445
Short name T63
Test name
Test status
Simulation time 10820778438 ps
CPU time 491.8 seconds
Started May 21 12:54:04 PM PDT 24
Finished May 21 01:02:19 PM PDT 24
Peak memory 256644 kb
Host smart-a43ae706-5663-4cbd-ade2-f75bdf29a517
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769735445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.1769735445 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_sideload/latest

Test location /workspace/coverage/default/7.kmac_smoke.1478845707
Short name T682
Test name
Test status
Simulation time 22109639039 ps
CPU time 67.05 seconds
Started May 21 12:53:53 PM PDT 24
Finished May 21 12:55:05 PM PDT 24
Peak memory 218884 kb
Host smart-f6825294-127a-41fc-b31a-b8f5d733dbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478845707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.1478845707 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_smoke/latest

Test location /workspace/coverage/default/7.kmac_stress_all.3805887994
Short name T966
Test name
Test status
Simulation time 81577160920 ps
CPU time 584.68 seconds
Started May 21 12:54:02 PM PDT 24
Finished May 21 01:03:49 PM PDT 24
Peak memory 275888 kb
Host smart-866a71ae-c856-4b2a-add0-2014b057eaee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3805887994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.3805887994 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac.2963208853
Short name T717
Test name
Test status
Simulation time 772652336 ps
CPU time 5.61 seconds
Started May 21 12:53:54 PM PDT 24
Finished May 21 12:54:04 PM PDT 24
Peak memory 226676 kb
Host smart-f0193f64-a69f-4393-b89e-72ca5ec7aee9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963208853 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.kmac_test_vectors_kmac.2963208853 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac_xof.2891757654
Short name T946
Test name
Test status
Simulation time 1031532930 ps
CPU time 6.55 seconds
Started May 21 12:53:38 PM PDT 24
Finished May 21 12:53:47 PM PDT 24
Peak memory 226664 kb
Host smart-c6b46d82-3e48-40c2-ab10-f855efd634e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891757654 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.kmac_test_vectors_kmac_xof.2891757654 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_224.1720826575
Short name T333
Test name
Test status
Simulation time 401967399130 ps
CPU time 2467.38 seconds
Started May 21 12:53:38 PM PDT 24
Finished May 21 01:34:48 PM PDT 24
Peak memory 393868 kb
Host smart-ed52936d-68fc-40ac-977c-17c7de7b758f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1720826575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_224.1720826575 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_256.3875722050
Short name T458
Test name
Test status
Simulation time 132155815740 ps
CPU time 2054.08 seconds
Started May 21 12:53:35 PM PDT 24
Finished May 21 01:27:52 PM PDT 24
Peak memory 390768 kb
Host smart-9492b558-32ef-4934-a556-0c430a459036
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3875722050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_256.3875722050 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_384.1234238274
Short name T669
Test name
Test status
Simulation time 287368658775 ps
CPU time 1782.32 seconds
Started May 21 12:53:36 PM PDT 24
Finished May 21 01:23:21 PM PDT 24
Peak memory 332424 kb
Host smart-beacc99a-bd2d-4d49-b53a-7bd5011e2c1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1234238274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_384.1234238274 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_512.44878539
Short name T1059
Test name
Test status
Simulation time 35031370062 ps
CPU time 1243.15 seconds
Started May 21 12:54:04 PM PDT 24
Finished May 21 01:14:50 PM PDT 24
Peak memory 299488 kb
Host smart-6ef90276-f085-4a29-8d4d-44ce7ecd2eab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=44878539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_512.44878539 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_128.4018111839
Short name T238
Test name
Test status
Simulation time 120715396747 ps
CPU time 4980.06 seconds
Started May 21 12:53:34 PM PDT 24
Finished May 21 02:16:37 PM PDT 24
Peak memory 655168 kb
Host smart-a2679f72-33f9-4475-8636-54343ea3c63e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4018111839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_128.4018111839 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_256.1590147658
Short name T465
Test name
Test status
Simulation time 211555648813 ps
CPU time 4525.29 seconds
Started May 21 12:53:38 PM PDT 24
Finished May 21 02:09:06 PM PDT 24
Peak memory 573320 kb
Host smart-459a522e-0119-46a3-bbcc-4e60ec928066
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1590147658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_256.1590147658 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/8.kmac_alert_test.3811386550
Short name T694
Test name
Test status
Simulation time 17550173 ps
CPU time 0.85 seconds
Started May 21 12:53:48 PM PDT 24
Finished May 21 12:53:52 PM PDT 24
Peak memory 218420 kb
Host smart-49fa1dd2-8e22-420e-b4e7-5d2f3454307d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811386550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.3811386550 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_alert_test/latest

Test location /workspace/coverage/default/8.kmac_app.807549052
Short name T614
Test name
Test status
Simulation time 12243374615 ps
CPU time 363.75 seconds
Started May 21 12:53:59 PM PDT 24
Finished May 21 01:00:05 PM PDT 24
Peak memory 251356 kb
Host smart-99e2ce75-a750-47ca-a9fa-874b669d8bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807549052 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.807549052 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_app/latest

Test location /workspace/coverage/default/8.kmac_app_with_partial_data.970050099
Short name T421
Test name
Test status
Simulation time 3260646354 ps
CPU time 42.82 seconds
Started May 21 12:53:55 PM PDT 24
Finished May 21 12:54:42 PM PDT 24
Peak memory 226876 kb
Host smart-13470718-251f-44fd-94d8-218cb00ea95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970050099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.970050099 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/8.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/8.kmac_burst_write.482097460
Short name T372
Test name
Test status
Simulation time 7967814010 ps
CPU time 751.37 seconds
Started May 21 12:53:40 PM PDT 24
Finished May 21 01:06:13 PM PDT 24
Peak memory 234100 kb
Host smart-c10f05bc-7e40-4045-9cbf-7f6e3a1ab148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482097460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.482097460 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_burst_write/latest

Test location /workspace/coverage/default/8.kmac_edn_timeout_error.86598792
Short name T844
Test name
Test status
Simulation time 22450611 ps
CPU time 0.93 seconds
Started May 21 12:54:02 PM PDT 24
Finished May 21 12:54:05 PM PDT 24
Peak memory 218420 kb
Host smart-b0e7ea80-7082-4514-8758-e08cf4c2e71b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=86598792 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.86598792 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/8.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_mode_error.1020221920
Short name T651
Test name
Test status
Simulation time 66135307 ps
CPU time 0.92 seconds
Started May 21 12:53:45 PM PDT 24
Finished May 21 12:53:49 PM PDT 24
Peak memory 220616 kb
Host smart-6877bdb4-a20e-4bb1-bf3a-af15ba686c16
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1020221920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.1020221920 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_refresh.2185065134
Short name T72
Test name
Test status
Simulation time 5581009104 ps
CPU time 129.32 seconds
Started May 21 12:53:41 PM PDT 24
Finished May 21 12:55:52 PM PDT 24
Peak memory 236424 kb
Host smart-343e6238-6fec-4ff0-b48c-b3680e408066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185065134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.2185065134 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/8.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/8.kmac_error.773211670
Short name T309
Test name
Test status
Simulation time 7839853037 ps
CPU time 44.45 seconds
Started May 21 12:53:41 PM PDT 24
Finished May 21 12:54:28 PM PDT 24
Peak memory 243316 kb
Host smart-b2b5cb61-dff5-4e22-93d6-d933d17e9c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773211670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.773211670 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_error/latest

Test location /workspace/coverage/default/8.kmac_key_error.1557526223
Short name T482
Test name
Test status
Simulation time 5007414170 ps
CPU time 10.47 seconds
Started May 21 12:54:08 PM PDT 24
Finished May 21 12:54:22 PM PDT 24
Peak memory 218652 kb
Host smart-d293f0bc-6eea-4fa4-8f72-4ecc7aee4779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557526223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.1557526223 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_key_error/latest

Test location /workspace/coverage/default/8.kmac_lc_escalation.3236107041
Short name T27
Test name
Test status
Simulation time 39491523 ps
CPU time 1.36 seconds
Started May 21 12:53:42 PM PDT 24
Finished May 21 12:53:46 PM PDT 24
Peak memory 218676 kb
Host smart-ec1efe15-29ff-45ab-ae05-62678fabbc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236107041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.3236107041 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/8.kmac_lc_escalation/latest

Test location /workspace/coverage/default/8.kmac_long_msg_and_output.4167168197
Short name T172
Test name
Test status
Simulation time 96254002804 ps
CPU time 3421.28 seconds
Started May 21 12:54:12 PM PDT 24
Finished May 21 01:51:16 PM PDT 24
Peak memory 500964 kb
Host smart-481bce35-ac51-44ef-8d4d-1e49fc73c051
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167168197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_an
d_output.4167168197 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/8.kmac_mubi.3900107631
Short name T688
Test name
Test status
Simulation time 18358999850 ps
CPU time 105.82 seconds
Started May 21 12:53:48 PM PDT 24
Finished May 21 12:55:37 PM PDT 24
Peak memory 233208 kb
Host smart-a559c706-7e57-4290-9e34-31316a8df116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900107631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.3900107631 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_mubi/latest

Test location /workspace/coverage/default/8.kmac_sideload.776118777
Short name T271
Test name
Test status
Simulation time 19562283981 ps
CPU time 413.17 seconds
Started May 21 12:54:10 PM PDT 24
Finished May 21 01:01:06 PM PDT 24
Peak memory 254164 kb
Host smart-a304c8ce-1869-4d8d-8cc7-e9b1b4b2710b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776118777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.776118777 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_sideload/latest

Test location /workspace/coverage/default/8.kmac_smoke.708691580
Short name T721
Test name
Test status
Simulation time 2248558892 ps
CPU time 55.32 seconds
Started May 21 12:54:03 PM PDT 24
Finished May 21 12:55:02 PM PDT 24
Peak memory 222560 kb
Host smart-aba4f95f-86f0-4b8e-b343-57a7627507b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708691580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.708691580 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_smoke/latest

Test location /workspace/coverage/default/8.kmac_stress_all.1877192428
Short name T323
Test name
Test status
Simulation time 46697834898 ps
CPU time 1902.95 seconds
Started May 21 12:53:46 PM PDT 24
Finished May 21 01:25:33 PM PDT 24
Peak memory 423352 kb
Host smart-b2b93d05-0927-48ad-9001-d46f093e25a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1877192428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.1877192428 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_stress_all/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac_xof.4055188000
Short name T805
Test name
Test status
Simulation time 384209775 ps
CPU time 5.8 seconds
Started May 21 12:54:07 PM PDT 24
Finished May 21 12:54:17 PM PDT 24
Peak memory 218628 kb
Host smart-ee3b9e3c-c3fc-4a97-8db5-e929ebb54afc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055188000 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.kmac_test_vectors_kmac_xof.4055188000 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_224.2462907997
Short name T720
Test name
Test status
Simulation time 338392454210 ps
CPU time 2154.66 seconds
Started May 21 12:53:50 PM PDT 24
Finished May 21 01:29:48 PM PDT 24
Peak memory 382040 kb
Host smart-49b1841c-fa7a-402b-be29-8f20426df450
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2462907997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_224.2462907997 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_256.4205460742
Short name T896
Test name
Test status
Simulation time 98431550586 ps
CPU time 2156.19 seconds
Started May 21 12:53:51 PM PDT 24
Finished May 21 01:29:52 PM PDT 24
Peak memory 392664 kb
Host smart-2be64083-b162-402d-83f1-204b9c7ed837
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4205460742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_256.4205460742 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_384.1633663284
Short name T960
Test name
Test status
Simulation time 34235420015 ps
CPU time 1573.27 seconds
Started May 21 12:53:40 PM PDT 24
Finished May 21 01:19:55 PM PDT 24
Peak memory 343024 kb
Host smart-3f554334-07f4-4da3-b562-0d73e3afa043
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1633663284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_384.1633663284 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_512.3768338295
Short name T337
Test name
Test status
Simulation time 42854114253 ps
CPU time 1038.78 seconds
Started May 21 12:53:40 PM PDT 24
Finished May 21 01:11:01 PM PDT 24
Peak memory 296840 kb
Host smart-151b2fe2-6be2-42bb-9cc6-477642f87225
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3768338295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_512.3768338295 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_shake_128.908203106
Short name T988
Test name
Test status
Simulation time 240693828527 ps
CPU time 5062.51 seconds
Started May 21 12:53:42 PM PDT 24
Finished May 21 02:18:07 PM PDT 24
Peak memory 652296 kb
Host smart-e11594c2-3220-4f1a-b23f-c7fdd09bc9d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=908203106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_128.908203106 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_shake_256.230020989
Short name T1021
Test name
Test status
Simulation time 229707052848 ps
CPU time 4487.79 seconds
Started May 21 12:53:50 PM PDT 24
Finished May 21 02:08:42 PM PDT 24
Peak memory 579228 kb
Host smart-da757af4-bf60-48b8-b443-33bd6b1c17b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=230020989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_256.230020989 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/9.kmac_alert_test.488443473
Short name T989
Test name
Test status
Simulation time 119799022 ps
CPU time 0.89 seconds
Started May 21 12:53:44 PM PDT 24
Finished May 21 12:53:48 PM PDT 24
Peak memory 218788 kb
Host smart-be33e1c8-1f30-4077-815c-980421de50c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488443473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.488443473 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/9.kmac_alert_test/latest

Test location /workspace/coverage/default/9.kmac_app.4270529370
Short name T17
Test name
Test status
Simulation time 49830537111 ps
CPU time 273.52 seconds
Started May 21 12:53:46 PM PDT 24
Finished May 21 12:58:23 PM PDT 24
Peak memory 246940 kb
Host smart-ec0c2d5e-7eb2-482b-8990-9c879f7d4e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270529370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.4270529370 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_app/latest

Test location /workspace/coverage/default/9.kmac_app_with_partial_data.2914862901
Short name T321
Test name
Test status
Simulation time 173794353113 ps
CPU time 164.95 seconds
Started May 21 12:54:05 PM PDT 24
Finished May 21 12:56:54 PM PDT 24
Peak memory 238356 kb
Host smart-ee4b66b5-dcf5-4216-883c-e276c9c96631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914862901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.2914862901 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/9.kmac_burst_write.2972160411
Short name T905
Test name
Test status
Simulation time 2213382907 ps
CPU time 110.93 seconds
Started May 21 12:53:40 PM PDT 24
Finished May 21 12:55:33 PM PDT 24
Peak memory 225420 kb
Host smart-5d08b0bc-a875-4ef9-9368-0b68efa5e642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972160411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.2972160411 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_burst_write/latest

Test location /workspace/coverage/default/9.kmac_edn_timeout_error.1973628399
Short name T3
Test name
Test status
Simulation time 50180597 ps
CPU time 1.03 seconds
Started May 21 12:53:57 PM PDT 24
Finished May 21 12:54:01 PM PDT 24
Peak memory 218420 kb
Host smart-10023166-a753-4e2d-8a3b-718ce4fb1798
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1973628399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.1973628399 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_mode_error.1155624128
Short name T914
Test name
Test status
Simulation time 3336663395 ps
CPU time 24.55 seconds
Started May 21 12:53:51 PM PDT 24
Finished May 21 12:54:20 PM PDT 24
Peak memory 226724 kb
Host smart-9333015c-3932-4ec8-ac11-493a4aadbf03
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1155624128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.1155624128 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_ready_error.752211267
Short name T927
Test name
Test status
Simulation time 3147456274 ps
CPU time 37.08 seconds
Started May 21 12:53:41 PM PDT 24
Finished May 21 12:54:20 PM PDT 24
Peak memory 226928 kb
Host smart-1c43f28d-fdc8-4929-bc46-5bc0d056d0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752211267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.752211267 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/9.kmac_error.2401316604
Short name T593
Test name
Test status
Simulation time 1658801761 ps
CPU time 31.6 seconds
Started May 21 12:53:55 PM PDT 24
Finished May 21 12:54:31 PM PDT 24
Peak memory 242944 kb
Host smart-a2d42058-9d6c-4cdf-8cd1-5fb20c5c55ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401316604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.2401316604 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_error/latest

Test location /workspace/coverage/default/9.kmac_key_error.1728843544
Short name T315
Test name
Test status
Simulation time 1091175343 ps
CPU time 9.24 seconds
Started May 21 12:53:56 PM PDT 24
Finished May 21 12:54:09 PM PDT 24
Peak memory 218536 kb
Host smart-e9613146-f963-40ca-a5c8-608052930911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728843544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.1728843544 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_key_error/latest

Test location /workspace/coverage/default/9.kmac_lc_escalation.1653388535
Short name T934
Test name
Test status
Simulation time 2963413134 ps
CPU time 23.18 seconds
Started May 21 12:53:44 PM PDT 24
Finished May 21 12:54:10 PM PDT 24
Peak memory 231080 kb
Host smart-55d5fbe3-d5dc-4099-97e7-ee61d342d6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653388535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.1653388535 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/9.kmac_lc_escalation/latest

Test location /workspace/coverage/default/9.kmac_long_msg_and_output.96004255
Short name T204
Test name
Test status
Simulation time 228805659506 ps
CPU time 1810.08 seconds
Started May 21 12:54:11 PM PDT 24
Finished May 21 01:24:24 PM PDT 24
Peak memory 375864 kb
Host smart-f981f467-80ed-4c0c-b120-6dedac1b0992
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96004255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and
_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_and_
output.96004255 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/9.kmac_mubi.1016120982
Short name T1006
Test name
Test status
Simulation time 7743862979 ps
CPU time 86.85 seconds
Started May 21 12:53:42 PM PDT 24
Finished May 21 12:55:12 PM PDT 24
Peak memory 232192 kb
Host smart-d621f3bc-16c7-497b-97b5-be28617ef0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016120982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.1016120982 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_mubi/latest

Test location /workspace/coverage/default/9.kmac_sideload.1497213891
Short name T311
Test name
Test status
Simulation time 7059623986 ps
CPU time 237.2 seconds
Started May 21 12:53:49 PM PDT 24
Finished May 21 12:57:50 PM PDT 24
Peak memory 241720 kb
Host smart-c2bc5e00-ce6f-433b-b014-a338a74d7c8e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497213891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.1497213891 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_sideload/latest

Test location /workspace/coverage/default/9.kmac_smoke.3184097408
Short name T365
Test name
Test status
Simulation time 2045875797 ps
CPU time 45.68 seconds
Started May 21 12:53:43 PM PDT 24
Finished May 21 12:54:31 PM PDT 24
Peak memory 226520 kb
Host smart-303de343-538a-4b25-97bd-22e03f3fe320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184097408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.3184097408 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_smoke/latest

Test location /workspace/coverage/default/9.kmac_stress_all.1216342440
Short name T484
Test name
Test status
Simulation time 957840875 ps
CPU time 50.69 seconds
Started May 21 12:54:00 PM PDT 24
Finished May 21 12:54:53 PM PDT 24
Peak memory 240036 kb
Host smart-56310037-2d0f-485f-b254-a14c4d31bfe0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1216342440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.1216342440 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_stress_all/latest

Test location /workspace/coverage/default/9.kmac_stress_all_with_rand_reset.1699698396
Short name T862
Test name
Test status
Simulation time 1033786352128 ps
CPU time 1740.41 seconds
Started May 21 12:54:03 PM PDT 24
Finished May 21 01:23:07 PM PDT 24
Peak memory 293708 kb
Host smart-84221006-f334-41d1-b3be-fe9a826ac023
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1699698396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all_with_rand_reset.1699698396 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac.475159653
Short name T576
Test name
Test status
Simulation time 222290428 ps
CPU time 5.93 seconds
Started May 21 12:53:42 PM PDT 24
Finished May 21 12:53:50 PM PDT 24
Peak memory 226676 kb
Host smart-b87a9895-6d89-49b8-87d1-7892441e6669
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475159653 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.kmac_test_vectors_kmac.475159653 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac_xof.958986292
Short name T684
Test name
Test status
Simulation time 640534368 ps
CPU time 5.93 seconds
Started May 21 12:53:42 PM PDT 24
Finished May 21 12:53:50 PM PDT 24
Peak memory 218604 kb
Host smart-4e62821e-4c40-40cc-949e-de17d48956b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958986292 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.kmac_test_vectors_kmac_xof.958986292 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_224.564341823
Short name T194
Test name
Test status
Simulation time 101572858002 ps
CPU time 2396.52 seconds
Started May 21 12:54:04 PM PDT 24
Finished May 21 01:34:05 PM PDT 24
Peak memory 398140 kb
Host smart-a0e4602b-20e6-4e01-a3dd-e42fa33908bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=564341823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_224.564341823 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_256.4144901489
Short name T105
Test name
Test status
Simulation time 381582768598 ps
CPU time 1983.64 seconds
Started May 21 12:53:48 PM PDT 24
Finished May 21 01:26:55 PM PDT 24
Peak memory 388044 kb
Host smart-eafaa1ec-4120-494e-b842-94ae8d1e1a5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4144901489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_256.4144901489 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_384.3681072403
Short name T400
Test name
Test status
Simulation time 209104206007 ps
CPU time 1667.17 seconds
Started May 21 12:53:56 PM PDT 24
Finished May 21 01:21:47 PM PDT 24
Peak memory 344132 kb
Host smart-2a37cf1c-5cfd-4138-8429-d10fbe40bd0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3681072403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_384.3681072403 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_512.2390789445
Short name T183
Test name
Test status
Simulation time 131539083286 ps
CPU time 1118.4 seconds
Started May 21 12:53:46 PM PDT 24
Finished May 21 01:12:29 PM PDT 24
Peak memory 300968 kb
Host smart-eb21fb74-97c4-4958-af94-8f88600ca5f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2390789445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_512.2390789445 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_128.2765892887
Short name T741
Test name
Test status
Simulation time 365107208657 ps
CPU time 5666.96 seconds
Started May 21 12:53:42 PM PDT 24
Finished May 21 02:28:12 PM PDT 24
Peak memory 659144 kb
Host smart-0a48cb01-091c-460c-a8d8-1cd0aa5ec7b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2765892887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_128.2765892887 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_256.4058327246
Short name T622
Test name
Test status
Simulation time 161068660555 ps
CPU time 5023.67 seconds
Started May 21 12:53:45 PM PDT 24
Finished May 21 02:17:33 PM PDT 24
Peak memory 584724 kb
Host smart-8f801e56-9d34-4df3-9558-ed382e71cbd0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4058327246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_256.4058327246 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_256/latest
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