Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	98857086	1			T1	460779		T2	8807		T3	3153
all_values[1]	98857086	1			T1	460779		T2	8807		T3	3153
all_values[2]	98857086	1			T1	460779		T2	8807		T3	3153

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

514441

1

T1

19

T2

244

T3

1

auto[1]

296056817

1

T1

138231

T2

26177

T3

9458

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

295066155

1

T1

137205

T2

26133

T3

9378

auto[1]

1505103

1

T1

10278

T2

288

T3

81

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	146028	1			T1	8		T2	241		T35	1
all_values[0]	auto[0]	auto[1]	1930	1			T1	8		T2	2		T35	2
all_values[0]	auto[1]	auto[0]	98209357	1			T1	457345		T2	8470		T3	3126
all_values[0]	auto[1]	auto[1]	499771	1			T1	3418		T2	94		T3	27
all_values[1]	auto[0]	auto[0]	157193	1			T1	1		T35	4		T7	281
all_values[1]	auto[0]	auto[1]	1515	1			T1	2		T35	3		T7	2
all_values[1]	auto[1]	auto[0]	98198192	1			T1	457352		T2	8711		T3	3126
all_values[1]	auto[1]	auto[1]	500186	1			T1	3424		T2	96		T3	27
all_values[2]	auto[0]	auto[0]	206230	1			T2	1		T3	1		T7	282
all_values[2]	auto[0]	auto[1]	1545	1			T7	2		T36	3		T38	3
all_values[2]	auto[1]	auto[0]	98149155	1			T1	457353		T2	8710		T3	3125
all_values[2]	auto[1]	auto[1]	500156	1			T1	3426		T2	96		T3	27