Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
315918 |
1 |
|
|
T1 |
2 |
|
T2 |
210 |
|
T3 |
56 |
auto[1] |
366748 |
1 |
|
|
T1 |
4528 |
|
T35 |
778 |
|
T36 |
4672 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
170483 |
1 |
|
|
T1 |
1228 |
|
T2 |
47 |
|
T3 |
10 |
lower_val |
169023 |
1 |
|
|
T1 |
1102 |
|
T2 |
60 |
|
T3 |
12 |
zero_val |
1834 |
1 |
|
|
T1 |
7 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
249830 |
1 |
|
|
T1 |
1166 |
|
T2 |
112 |
|
T3 |
30 |
lower_val |
248998 |
1 |
|
|
T1 |
1076 |
|
T2 |
98 |
|
T3 |
26 |
zero_val |
183838 |
1 |
|
|
T1 |
2288 |
|
T35 |
436 |
|
T36 |
2418 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
39055 |
1 |
|
|
T2 |
26 |
|
T3 |
6 |
|
T7 |
32 |
higher_val |
higher_val |
auto[1] |
23157 |
1 |
|
|
T1 |
322 |
|
T35 |
43 |
|
T36 |
311 |
higher_val |
lower_val |
auto[0] |
39586 |
1 |
|
|
T2 |
21 |
|
T3 |
4 |
|
T7 |
39 |
higher_val |
lower_val |
auto[1] |
22745 |
1 |
|
|
T1 |
293 |
|
T35 |
41 |
|
T36 |
259 |
higher_val |
zero_val |
auto[0] |
91 |
1 |
|
|
T95 |
1 |
|
T202 |
1 |
|
T43 |
1 |
higher_val |
zero_val |
auto[1] |
45849 |
1 |
|
|
T1 |
613 |
|
T35 |
108 |
|
T36 |
614 |
lower_val |
higher_val |
auto[0] |
39314 |
1 |
|
|
T2 |
29 |
|
T3 |
3 |
|
T7 |
37 |
lower_val |
higher_val |
auto[1] |
22732 |
1 |
|
|
T1 |
275 |
|
T35 |
48 |
|
T36 |
278 |
lower_val |
lower_val |
auto[0] |
39125 |
1 |
|
|
T2 |
31 |
|
T3 |
9 |
|
T7 |
39 |
lower_val |
lower_val |
auto[1] |
22329 |
1 |
|
|
T1 |
242 |
|
T35 |
44 |
|
T36 |
262 |
lower_val |
zero_val |
auto[0] |
78 |
1 |
|
|
T1 |
1 |
|
T35 |
1 |
|
T203 |
1 |
lower_val |
zero_val |
auto[1] |
45445 |
1 |
|
|
T1 |
584 |
|
T35 |
117 |
|
T36 |
602 |
zero_val |
higher_val |
auto[0] |
550 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T7 |
1 |
zero_val |
higher_val |
auto[1] |
150 |
1 |
|
|
T1 |
2 |
|
T36 |
1 |
|
T63 |
2 |
zero_val |
lower_val |
auto[0] |
509 |
1 |
|
|
T20 |
1 |
|
T17 |
1 |
|
T204 |
1 |
zero_val |
lower_val |
auto[1] |
133 |
1 |
|
|
T36 |
2 |
|
T203 |
1 |
|
T205 |
2 |
zero_val |
zero_val |
auto[0] |
268 |
1 |
|
|
T1 |
1 |
|
T35 |
1 |
|
T36 |
1 |
zero_val |
zero_val |
auto[1] |
224 |
1 |
|
|
T1 |
4 |
|
T36 |
1 |
|
T38 |
4 |