Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	98857086	1			T1	460779		T2	8807		T3	3153
all_pins[1]	98857086	1			T1	460779		T2	8807		T3	3153
all_pins[2]	98857086	1			T1	460779		T2	8807		T3	3153

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	295786789	1			T1	137891		T2	26319		T3	9432
values[0x1]	784469	1			T1	3418		T2	102		T3	27
transitions[0x0=>0x1]	782570	1			T1	3418		T2	102		T3	27
transitions[0x1=>0x0]	782594	1			T1	3418		T2	102		T3	27

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98357315	1			T1	457361		T2	8713		T3	3126
all_pins[0]	values[0x1]	499771	1			T1	3418		T2	94		T3	27
all_pins[0]	transitions[0x0=>0x1]	499757	1			T1	3418		T2	94		T3	27
all_pins[0]	transitions[0x1=>0x0]	6019	1			T2	8		T20	47		T42	1
all_pins[1]	values[0x0]	98851053	1			T1	460779		T2	8799		T3	3153
all_pins[1]	values[0x1]	6033	1			T2	8		T20	47		T42	1
all_pins[1]	transitions[0x0=>0x1]	5821	1			T2	8		T20	47		T42	1
all_pins[1]	transitions[0x1=>0x0]	278453	1			T20	597		T17	1679		T21	1911
all_pins[2]	values[0x0]	98578421	1			T1	460779		T2	8807		T3	3153
all_pins[2]	values[0x1]	278665	1			T20	597		T17	1679		T21	1911
all_pins[2]	transitions[0x0=>0x1]	276992	1			T20	597		T17	1679		T21	1911
all_pins[2]	transitions[0x1=>0x0]	498122	1			T1	3418		T2	94		T3	27