Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	624	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5244	1			T2	8		T3	3		T7	22
len_601_800	11743	1			T2	28		T3	7		T7	35
len_401_600	7789	1			T2	13		T3	5		T7	16
len_201_400	15913	1			T1	251		T2	8		T3	1
len_65_200	72690	1			T1	680		T2	4		T7	3
len_min_for_xof_require_squeeze	984	1			T1	10		T36	9		T63	9
len_keccak_block_sizes[72]	746	1			T1	5		T36	9		T63	9
len_keccak_block_sizes[104]	740	1			T1	5		T36	9		T63	9
len_keccak_block_sizes[136]	754	1			T1	5		T36	9		T63	9
len_keccak_block_sizes[144]	275	1			T1	5		T206	5		T91	5
len_keccak_block_sizes[168]	273	1			T1	5		T206	5		T91	5
len_datapath_width	14063	1			T1	5		T36	9		T20	1
len_2_63	211694	1			T1	1329		T2	43		T3	12
len_1	43	1			T207	1		T208	1		T209	1