Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10297582 |
1 |
|
|
T1 |
47900 |
|
T2 |
11859 |
|
T3 |
3286 |
auto[1] |
10297545 |
1 |
|
|
T1 |
47900 |
|
T2 |
11859 |
|
T3 |
3286 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
20362685 |
1 |
|
|
T1 |
93928 |
|
T2 |
23628 |
|
T3 |
6546 |
triple_byte_access |
77484 |
1 |
|
|
T1 |
620 |
|
T2 |
32 |
|
T3 |
16 |
halfword_access |
77638 |
1 |
|
|
T1 |
632 |
|
T2 |
26 |
|
T3 |
6 |
byte_access |
77320 |
1 |
|
|
T1 |
620 |
|
T2 |
32 |
|
T3 |
4 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10181361 |
1 |
|
|
T1 |
46964 |
|
T2 |
11814 |
|
T3 |
3273 |
auto[0] |
triple_byte_access |
38742 |
1 |
|
|
T1 |
310 |
|
T2 |
16 |
|
T3 |
8 |
auto[0] |
halfword_access |
38819 |
1 |
|
|
T1 |
316 |
|
T2 |
13 |
|
T3 |
3 |
auto[0] |
byte_access |
38660 |
1 |
|
|
T1 |
310 |
|
T2 |
16 |
|
T3 |
2 |
auto[1] |
word_access |
10181324 |
1 |
|
|
T1 |
46964 |
|
T2 |
11814 |
|
T3 |
3273 |
auto[1] |
triple_byte_access |
38742 |
1 |
|
|
T1 |
310 |
|
T2 |
16 |
|
T3 |
8 |
auto[1] |
halfword_access |
38819 |
1 |
|
|
T1 |
316 |
|
T2 |
13 |
|
T3 |
3 |
auto[1] |
byte_access |
38660 |
1 |
|
|
T1 |
310 |
|
T2 |
16 |
|
T3 |
2 |