Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100583548	1			T1	224673		T3	13938		T16	24423
all_values[1]	100583548	1			T1	224673		T3	13938		T16	24423
all_values[2]	100583548	1			T1	224673		T3	13938		T16	24423

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

630936

1

T1

15

T3

384

T33

11

auto[1]

301119708

1

T1

674004

T3

41430

T16

73269

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300234072

1

T1

672225

T3

41388

T16

72543

auto[1]

1516572

1

T1

1794

T3

426

T16

726

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	229159	1			T6	260		T37	5		T38	1
all_values[0]	auto[0]	auto[1]	2058	1			T6	12		T37	6		T38	2
all_values[0]	auto[1]	auto[0]	99848865	1			T1	224075		T3	13796		T16	24181
all_values[0]	auto[1]	auto[1]	503466	1			T1	598		T3	142		T16	242
all_values[1]	auto[0]	auto[0]	211847	1			T1	9		T3	191		T33	7
all_values[1]	auto[0]	auto[1]	1544	1			T1	6		T3	1		T33	4
all_values[1]	auto[1]	auto[0]	99866177	1			T1	224066		T3	13605		T16	24181
all_values[1]	auto[1]	auto[1]	503980	1			T1	592		T3	141		T16	242
all_values[2]	auto[0]	auto[0]	184736	1			T3	191		T6	111		T38	16
all_values[2]	auto[0]	auto[1]	1592	1			T3	1		T6	2		T38	10
all_values[2]	auto[1]	auto[0]	99893288	1			T1	224075		T3	13605		T16	24181
all_values[2]	auto[1]	auto[1]	503932	1			T1	598		T3	141		T16	242