Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
317958 |
1 |
|
|
T1 |
780 |
|
T3 |
230 |
|
T16 |
310 |
auto[1] |
369566 |
1 |
|
|
T6 |
166 |
|
T38 |
4528 |
|
T34 |
16 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
172300 |
1 |
|
|
T1 |
197 |
|
T3 |
50 |
|
T16 |
91 |
lower_val |
171188 |
1 |
|
|
T1 |
172 |
|
T3 |
56 |
|
T16 |
64 |
zero_val |
1802 |
1 |
|
|
T1 |
5 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
251560 |
1 |
|
|
T1 |
412 |
|
T3 |
118 |
|
T16 |
156 |
lower_val |
250860 |
1 |
|
|
T1 |
368 |
|
T3 |
112 |
|
T16 |
154 |
zero_val |
185104 |
1 |
|
|
T6 |
80 |
|
T38 |
2266 |
|
T34 |
12 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
40049 |
1 |
|
|
T1 |
106 |
|
T3 |
25 |
|
T16 |
49 |
higher_val |
higher_val |
auto[1] |
23208 |
1 |
|
|
T6 |
11 |
|
T38 |
321 |
|
T48 |
35 |
higher_val |
lower_val |
auto[0] |
39716 |
1 |
|
|
T1 |
91 |
|
T3 |
25 |
|
T16 |
42 |
higher_val |
lower_val |
auto[1] |
23121 |
1 |
|
|
T6 |
10 |
|
T38 |
264 |
|
T34 |
1 |
higher_val |
zero_val |
auto[0] |
92 |
1 |
|
|
T67 |
1 |
|
T14 |
2 |
|
T202 |
1 |
higher_val |
zero_val |
auto[1] |
46114 |
1 |
|
|
T6 |
16 |
|
T38 |
582 |
|
T34 |
4 |
lower_val |
higher_val |
auto[0] |
39390 |
1 |
|
|
T1 |
90 |
|
T3 |
31 |
|
T16 |
34 |
lower_val |
higher_val |
auto[1] |
23185 |
1 |
|
|
T6 |
7 |
|
T38 |
303 |
|
T34 |
1 |
lower_val |
lower_val |
auto[0] |
39111 |
1 |
|
|
T1 |
82 |
|
T3 |
25 |
|
T16 |
30 |
lower_val |
lower_val |
auto[1] |
22928 |
1 |
|
|
T6 |
12 |
|
T38 |
243 |
|
T48 |
25 |
lower_val |
zero_val |
auto[0] |
76 |
1 |
|
|
T6 |
1 |
|
T7 |
2 |
|
T144 |
1 |
lower_val |
zero_val |
auto[1] |
46498 |
1 |
|
|
T6 |
19 |
|
T38 |
544 |
|
T34 |
1 |
zero_val |
higher_val |
auto[0] |
499 |
1 |
|
|
T1 |
2 |
|
T3 |
1 |
|
T16 |
1 |
zero_val |
higher_val |
auto[1] |
124 |
1 |
|
|
T6 |
1 |
|
T38 |
1 |
|
T48 |
1 |
zero_val |
lower_val |
auto[0] |
560 |
1 |
|
|
T1 |
3 |
|
T6 |
1 |
|
T38 |
1 |
zero_val |
lower_val |
auto[1] |
149 |
1 |
|
|
T38 |
1 |
|
T7 |
2 |
|
T17 |
1 |
zero_val |
zero_val |
auto[0] |
253 |
1 |
|
|
T67 |
1 |
|
T18 |
1 |
|
T202 |
1 |
zero_val |
zero_val |
auto[1] |
217 |
1 |
|
|
T38 |
2 |
|
T48 |
1 |
|
T39 |
1 |