Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100583548	1			T1	224673		T3	13938		T16	24423
all_pins[1]	100583548	1			T1	224673		T3	13938		T16	24423
all_pins[2]	100583548	1			T1	224673		T3	13938		T16	24423

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	300907914	1			T1	673421		T3	41672		T16	73027
values[0x1]	842730	1			T1	598		T3	142		T16	242
transitions[0x0=>0x1]	840268	1			T1	598		T3	142		T16	242
transitions[0x1=>0x0]	840289	1			T1	598		T3	142		T16	242

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100080082	1			T1	224075		T3	13796		T16	24181
all_pins[0]	values[0x1]	503466	1			T1	598		T3	142		T16	242
all_pins[0]	transitions[0x0=>0x1]	503452	1			T1	598		T3	142		T16	242
all_pins[0]	transitions[0x1=>0x0]	7221	1			T6	58		T41	77		T67	1
all_pins[1]	values[0x0]	100576313	1			T1	224673		T3	13938		T16	24423
all_pins[1]	values[0x1]	7235	1			T6	58		T41	77		T67	1
all_pins[1]	transitions[0x0=>0x1]	6846	1			T6	58		T41	77		T67	1
all_pins[1]	transitions[0x1=>0x0]	331640	1			T7	11039		T14	5588		T21	18
all_pins[2]	values[0x0]	100251519	1			T1	224673		T3	13938		T16	24423
all_pins[2]	values[0x1]	332029	1			T7	11039		T14	5601		T21	18
all_pins[2]	transitions[0x0=>0x1]	329970	1			T7	10968		T14	5564		T21	18
all_pins[2]	transitions[0x1=>0x0]	501428	1			T1	598		T3	142		T16	242