Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	748	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5734	1			T3	15		T16	16		T6	24
len_601_800	12790	1			T3	37		T16	64		T6	47
len_401_600	8558	1			T3	21		T16	32		T6	30
len_201_400	16316	1			T3	11		T16	21		T6	12
len_65_200	72901	1			T3	5		T16	12		T6	10
len_min_for_xof_require_squeeze	1003	1			T3	1		T38	10		T41	1
len_keccak_block_sizes[72]	749	1			T38	5		T39	1		T143	1
len_keccak_block_sizes[104]	755	1			T38	5		T143	2		T14	1
len_keccak_block_sizes[136]	748	1			T38	5		T39	2		T143	2
len_keccak_block_sizes[144]	283	1			T3	1		T38	5		T7	1
len_keccak_block_sizes[168]	284	1			T38	5		T39	1		T22	1
len_datapath_width	14148	1			T3	1		T6	9		T38	5
len_2_63	210871	1			T1	390		T3	22		T16	7
len_1	56	1			T7	3		T69	1		T144	1