Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10871031 |
1 |
|
|
T1 |
2730 |
|
T3 |
16580 |
|
T16 |
24922 |
auto[1] |
10870968 |
1 |
|
|
T1 |
2730 |
|
T3 |
16580 |
|
T16 |
24922 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21504484 |
1 |
|
|
T1 |
5460 |
|
T3 |
33016 |
|
T16 |
49612 |
triple_byte_access |
78905 |
1 |
|
|
T3 |
52 |
|
T16 |
70 |
|
T6 |
54 |
halfword_access |
79580 |
1 |
|
|
T3 |
38 |
|
T16 |
76 |
|
T6 |
76 |
byte_access |
79030 |
1 |
|
|
T3 |
54 |
|
T16 |
86 |
|
T6 |
68 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10752273 |
1 |
|
|
T1 |
2730 |
|
T3 |
16508 |
|
T16 |
24806 |
auto[0] |
triple_byte_access |
39453 |
1 |
|
|
T3 |
26 |
|
T16 |
35 |
|
T6 |
27 |
auto[0] |
halfword_access |
39790 |
1 |
|
|
T3 |
19 |
|
T16 |
38 |
|
T6 |
38 |
auto[0] |
byte_access |
39515 |
1 |
|
|
T3 |
27 |
|
T16 |
43 |
|
T6 |
34 |
auto[1] |
word_access |
10752211 |
1 |
|
|
T1 |
2730 |
|
T3 |
16508 |
|
T16 |
24806 |
auto[1] |
triple_byte_access |
39452 |
1 |
|
|
T3 |
26 |
|
T16 |
35 |
|
T6 |
27 |
auto[1] |
halfword_access |
39790 |
1 |
|
|
T3 |
19 |
|
T16 |
38 |
|
T6 |
38 |
auto[1] |
byte_access |
39515 |
1 |
|
|
T3 |
27 |
|
T16 |
43 |
|
T6 |
34 |