Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	98764415	1			T1	21662		T2	14754		T3	1444
all_values[1]	98764415	1			T1	21662		T2	14754		T3	1444
all_values[2]	98764415	1			T1	21662		T2	14754		T3	1444

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

594570

1

T1

1376

T2

299

T3

420

auto[1]

295698675

1

T1

63610

T2

43963

T3

3912

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

294783075

1

T1

64377

T2

43821

T3

4296

auto[1]

1510170

1

T1

609

T2

441

T3

36

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	179810	1			T1	920		T35	1		T16	20
all_values[0]	auto[0]	auto[1]	1948	1			T1	10		T35	2		T16	8
all_values[0]	auto[1]	auto[0]	98081215	1			T1	20539		T2	14607		T3	1432
all_values[0]	auto[1]	auto[1]	501442	1			T1	193		T2	147		T3	12
all_values[1]	auto[0]	auto[0]	187871	1			T1	221		T2	295		T31	2
all_values[1]	auto[0]	auto[1]	1529	1			T1	2		T2	2		T31	1
all_values[1]	auto[1]	auto[0]	98073154	1			T1	21238		T2	14312		T3	1432
all_values[1]	auto[1]	auto[1]	501861	1			T1	201		T2	145		T3	12
all_values[2]	auto[0]	auto[0]	221787	1			T1	221		T2	2		T3	418
all_values[2]	auto[0]	auto[1]	1625	1			T1	2		T3	2		T32	4
all_values[2]	auto[1]	auto[0]	98039238	1			T1	21238		T2	14605		T3	1014
all_values[2]	auto[1]	auto[1]	501765	1			T1	201		T2	147		T3	10