Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
328310 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
357028 |
1 |
|
|
T1 |
286 |
|
T2 |
250 |
|
T3 |
30 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
172273 |
1 |
|
|
T1 |
70 |
|
T2 |
62 |
|
T3 |
4 |
lower_val |
169245 |
1 |
|
|
T1 |
86 |
|
T2 |
54 |
|
T3 |
6 |
zero_val |
1731 |
1 |
|
|
T1 |
1 |
|
T2 |
3 |
|
T3 |
3 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
254046 |
1 |
|
|
T1 |
76 |
|
T2 |
52 |
|
T3 |
10 |
lower_val |
252870 |
1 |
|
|
T1 |
68 |
|
T2 |
72 |
|
T3 |
6 |
zero_val |
178422 |
1 |
|
|
T1 |
144 |
|
T2 |
128 |
|
T3 |
16 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
41174 |
1 |
|
|
T31 |
64 |
|
T32 |
1 |
|
T10 |
1 |
higher_val |
higher_val |
auto[1] |
22574 |
1 |
|
|
T1 |
21 |
|
T2 |
13 |
|
T32 |
35 |
higher_val |
lower_val |
auto[0] |
41002 |
1 |
|
|
T31 |
59 |
|
T16 |
17 |
|
T49 |
62 |
higher_val |
lower_val |
auto[1] |
22471 |
1 |
|
|
T1 |
16 |
|
T2 |
17 |
|
T3 |
1 |
higher_val |
zero_val |
auto[0] |
88 |
1 |
|
|
T1 |
1 |
|
T61 |
1 |
|
T180 |
1 |
higher_val |
zero_val |
auto[1] |
44964 |
1 |
|
|
T1 |
32 |
|
T2 |
32 |
|
T3 |
3 |
lower_val |
higher_val |
auto[0] |
40647 |
1 |
|
|
T31 |
76 |
|
T16 |
22 |
|
T49 |
57 |
lower_val |
higher_val |
auto[1] |
22260 |
1 |
|
|
T1 |
20 |
|
T2 |
16 |
|
T3 |
4 |
lower_val |
lower_val |
auto[0] |
40321 |
1 |
|
|
T2 |
1 |
|
T31 |
66 |
|
T16 |
18 |
lower_val |
lower_val |
auto[1] |
22177 |
1 |
|
|
T1 |
18 |
|
T2 |
17 |
|
T32 |
42 |
lower_val |
zero_val |
auto[0] |
71 |
1 |
|
|
T63 |
1 |
|
T181 |
1 |
|
T52 |
1 |
lower_val |
zero_val |
auto[1] |
43769 |
1 |
|
|
T1 |
48 |
|
T2 |
20 |
|
T3 |
2 |
zero_val |
higher_val |
auto[0] |
531 |
1 |
|
|
T31 |
1 |
|
T32 |
1 |
|
T10 |
1 |
zero_val |
higher_val |
auto[1] |
138 |
1 |
|
|
T38 |
1 |
|
T13 |
1 |
|
T60 |
2 |
zero_val |
lower_val |
auto[0] |
479 |
1 |
|
|
T2 |
1 |
|
T16 |
2 |
|
T36 |
1 |
zero_val |
lower_val |
auto[1] |
132 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T35 |
1 |
zero_val |
zero_val |
auto[0] |
257 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T35 |
1 |
zero_val |
zero_val |
auto[1] |
194 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T35 |
3 |