Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	98764415	1			T1	21662		T2	14754		T3	1444
all_pins[1]	98764415	1			T1	21662		T2	14754		T3	1444
all_pins[2]	98764415	1			T1	21662		T2	14754		T3	1444

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	295463338	1			T1	64314		T2	44084		T3	4320
values[0x1]	829907	1			T1	672		T2	178		T3	12
transitions[0x0=>0x1]	827537	1			T1	672		T2	178		T3	12
transitions[0x1=>0x0]	827553	1			T1	672		T2	178		T3	12

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98262973	1			T1	21469		T2	14607		T3	1432
all_pins[0]	values[0x1]	501442	1			T1	193		T2	147		T3	12
all_pins[0]	transitions[0x0=>0x1]	501428	1			T1	193		T2	147		T3	12
all_pins[0]	transitions[0x1=>0x0]	5540	1			T2	31		T16	9		T36	35
all_pins[1]	values[0x0]	98758861	1			T1	21662		T2	14723		T3	1444
all_pins[1]	values[0x1]	5554	1			T2	31		T16	9		T36	35
all_pins[1]	transitions[0x0=>0x1]	5171	1			T2	31		T16	9		T36	35
all_pins[1]	transitions[0x1=>0x0]	322528	1			T1	479		T19	316		T13	10761
all_pins[2]	values[0x0]	98441504	1			T1	21183		T2	14754		T3	1444
all_pins[2]	values[0x1]	322911	1			T1	479		T19	316		T13	10779
all_pins[2]	transitions[0x0=>0x1]	320938	1			T1	479		T19	316		T13	10711
all_pins[2]	transitions[0x1=>0x0]	499485	1			T1	193		T2	147		T3	12