Summary for Variable in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for in_app_keymgr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
336540 |
1 |
|
|
T1 |
145 |
|
T2 |
135 |
|
T3 |
20 |
auto[1] |
3398 |
1 |
|
|
T1 |
2 |
|
T2 |
20 |
|
T3 |
3 |
Summary for Variable kmac_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
301980 |
1 |
|
|
T1 |
41 |
|
T2 |
71 |
|
T3 |
15 |
auto[1] |
37958 |
1 |
|
|
T1 |
106 |
|
T2 |
84 |
|
T3 |
8 |
Summary for Variable sideload
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sideload
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
325292 |
1 |
|
|
T1 |
127 |
|
T2 |
108 |
|
T3 |
19 |
auto[1] |
14646 |
1 |
|
|
T1 |
20 |
|
T2 |
47 |
|
T3 |
4 |
Summary for Cross sideload_cross
Samples crossed: sideload kmac_mode in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins for sideload_cross
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sw_kmac_valid_sideload |
14646 |
1 |
|
|
T1 |
20 |
|
T2 |
47 |
|
T3 |
4 |
sw_kmac_invalid_sideload |
325292 |
1 |
|
|
T1 |
127 |
|
T2 |
108 |
|
T3 |
19 |
app_valid_sideload |
14646 |
1 |
|
|
T1 |
20 |
|
T2 |
47 |
|
T3 |
4 |
app_invalid_sideload |
325292 |
1 |
|
|
T1 |
127 |
|
T2 |
108 |
|
T3 |
19 |