Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10709221 |
1 |
|
|
T1 |
22662 |
|
T2 |
17891 |
|
T3 |
1751 |
auto[1] |
10709210 |
1 |
|
|
T1 |
22662 |
|
T2 |
17891 |
|
T3 |
1751 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21183119 |
1 |
|
|
T1 |
45130 |
|
T2 |
35622 |
|
T3 |
3494 |
triple_byte_access |
78322 |
1 |
|
|
T1 |
62 |
|
T2 |
48 |
|
T3 |
2 |
halfword_access |
78710 |
1 |
|
|
T1 |
78 |
|
T2 |
62 |
|
T3 |
4 |
byte_access |
78280 |
1 |
|
|
T1 |
54 |
|
T2 |
50 |
|
T3 |
2 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10591565 |
1 |
|
|
T1 |
22565 |
|
T2 |
17811 |
|
T3 |
1747 |
auto[0] |
triple_byte_access |
39161 |
1 |
|
|
T1 |
31 |
|
T2 |
24 |
|
T3 |
1 |
auto[0] |
halfword_access |
39355 |
1 |
|
|
T1 |
39 |
|
T2 |
31 |
|
T3 |
2 |
auto[0] |
byte_access |
39140 |
1 |
|
|
T1 |
27 |
|
T2 |
25 |
|
T3 |
1 |
auto[1] |
word_access |
10591554 |
1 |
|
|
T1 |
22565 |
|
T2 |
17811 |
|
T3 |
1747 |
auto[1] |
triple_byte_access |
39161 |
1 |
|
|
T1 |
31 |
|
T2 |
24 |
|
T3 |
1 |
auto[1] |
halfword_access |
39355 |
1 |
|
|
T1 |
39 |
|
T2 |
31 |
|
T3 |
2 |
auto[1] |
byte_access |
39140 |
1 |
|
|
T1 |
27 |
|
T2 |
25 |
|
T3 |
1 |