Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	98896684	1			T1	4		T2	10764		T3	74146
all_values[1]	98896684	1			T1	4		T2	10764		T3	74146
all_values[2]	98896684	1			T1	4		T2	10764		T3	74146

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

546061

1

T1

4

T2

398

T3

2247

auto[1]

296143991

1

T1

8

T2

31894

T3

220191

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

295178304

1

T1

12

T2

31947

T3

220266

auto[1]

1511748

1

T2

345

T3

2172

T7

264

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	209098	1			T2	197		T3	432		T31	1
all_values[0]	auto[0]	auto[1]	2171	1			T2	2		T3	24		T31	2
all_values[0]	auto[1]	auto[0]	98183670	1			T1	4		T2	10452		T3	72990
all_values[0]	auto[1]	auto[1]	501745	1			T2	113		T3	700		T7	88
all_values[1]	auto[0]	auto[0]	147391	1			T1	4		T3	516		T31	1
all_values[1]	auto[0]	auto[1]	1506	1			T3	8		T31	2		T32	4
all_values[1]	auto[1]	auto[0]	98245377	1			T2	10649		T3	72906		T7	8303
all_values[1]	auto[1]	auto[1]	502410	1			T2	115		T3	716		T7	88
all_values[2]	auto[0]	auto[0]	184317	1			T2	197		T3	1240		T7	289
all_values[2]	auto[0]	auto[1]	1578	1			T2	2		T3	27		T7	1
all_values[2]	auto[1]	auto[0]	98208451	1			T1	4		T2	10452		T3	72182
all_values[2]	auto[1]	auto[1]	502338	1			T2	113		T3	697		T7	87