Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
349310 |
1 |
|
|
T1 |
2 |
|
T2 |
144 |
|
T3 |
632 |
auto[1] |
336356 |
1 |
|
|
T3 |
384 |
|
T7 |
168 |
|
T31 |
746 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
171619 |
1 |
|
|
T1 |
1 |
|
T2 |
46 |
|
T3 |
237 |
lower_val |
169355 |
1 |
|
|
T2 |
41 |
|
T3 |
237 |
|
T7 |
47 |
zero_val |
1883 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
11 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
258342 |
1 |
|
|
T1 |
2 |
|
T2 |
62 |
|
T3 |
396 |
lower_val |
258822 |
1 |
|
|
T2 |
82 |
|
T3 |
422 |
|
T7 |
42 |
zero_val |
168502 |
1 |
|
|
T3 |
198 |
|
T7 |
84 |
|
T31 |
368 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
43558 |
1 |
|
|
T1 |
1 |
|
T2 |
18 |
|
T3 |
76 |
higher_val |
higher_val |
auto[1] |
21032 |
1 |
|
|
T3 |
20 |
|
T7 |
10 |
|
T31 |
53 |
higher_val |
lower_val |
auto[0] |
43750 |
1 |
|
|
T2 |
28 |
|
T3 |
63 |
|
T32 |
22 |
higher_val |
lower_val |
auto[1] |
21274 |
1 |
|
|
T3 |
38 |
|
T7 |
6 |
|
T31 |
49 |
higher_val |
zero_val |
auto[0] |
95 |
1 |
|
|
T3 |
2 |
|
T14 |
1 |
|
T184 |
1 |
higher_val |
zero_val |
auto[1] |
41910 |
1 |
|
|
T3 |
38 |
|
T7 |
26 |
|
T31 |
104 |
lower_val |
higher_val |
auto[0] |
43158 |
1 |
|
|
T2 |
16 |
|
T3 |
65 |
|
T32 |
22 |
lower_val |
higher_val |
auto[1] |
20619 |
1 |
|
|
T3 |
19 |
|
T7 |
12 |
|
T31 |
35 |
lower_val |
lower_val |
auto[0] |
43254 |
1 |
|
|
T2 |
25 |
|
T3 |
83 |
|
T32 |
14 |
lower_val |
lower_val |
auto[1] |
20670 |
1 |
|
|
T3 |
23 |
|
T7 |
13 |
|
T31 |
46 |
lower_val |
zero_val |
auto[0] |
77 |
1 |
|
|
T3 |
1 |
|
T14 |
2 |
|
T5 |
1 |
lower_val |
zero_val |
auto[1] |
41577 |
1 |
|
|
T3 |
46 |
|
T7 |
22 |
|
T31 |
77 |
zero_val |
higher_val |
auto[0] |
593 |
1 |
|
|
T1 |
1 |
|
T3 |
4 |
|
T32 |
1 |
zero_val |
higher_val |
auto[1] |
137 |
1 |
|
|
T3 |
1 |
|
T14 |
2 |
|
T43 |
1 |
zero_val |
lower_val |
auto[0] |
541 |
1 |
|
|
T2 |
1 |
|
T3 |
2 |
|
T31 |
1 |
zero_val |
lower_val |
auto[1] |
155 |
1 |
|
|
T3 |
2 |
|
T66 |
1 |
|
T14 |
1 |
zero_val |
zero_val |
auto[0] |
266 |
1 |
|
|
T3 |
2 |
|
T7 |
1 |
|
T14 |
2 |
zero_val |
zero_val |
auto[1] |
191 |
1 |
|
|
T66 |
1 |
|
T14 |
3 |
|
T43 |
1 |