Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10149	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	9057	1			T3	20		T31	19		T35	40
len_5001_7500	14491	1			T3	39		T31	18		T35	98
len_2501_5000	9137	1			T3	7		T31	18		T35	21
len_1025_2500	5324	1			T3	5		T31	11		T35	9
len_769_1024	6148	1			T2	14		T3	45		T7	16
len_513_768	6676	1			T2	22		T3	58		T7	9
len_257_512	20530	1			T2	16		T3	55		T7	14
len_0_256	254252	1			T2	20		T3	233		T7	19
len_keccak_block_sizes[72]	718	1			T3	1		T31	2		T66	2
len_keccak_block_sizes[104]	608	1			T31	2		T66	2		T43	2
len_keccak_block_sizes[136]	513	1			T31	2		T42	3		T44	2
len_keccak_block_sizes[144]	430	1			T3	1		T42	3		T44	2
len_keccak_block_sizes[168]	316	1			T42	3		T117	3		T137	1
len_1	758	1			T3	1		T31	2		T32	3
len_0	1226	1			T3	4		T31	2		T32	4