Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	98896684	1			T1	4		T2	10764		T3	74146
all_pins[1]	98896684	1			T1	4		T2	10764		T3	74146
all_pins[2]	98896684	1			T1	4		T2	10764		T3	74146

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	295897483	1			T1	12		T2	32148		T3	212851
values[0x1]	792569	1			T2	144		T3	9587		T7	8161
transitions[0x0=>0x1]	790622	1			T2	144		T3	9509		T7	8074
transitions[0x1=>0x0]	790654	1			T2	144		T3	9509		T7	8074

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98394939	1			T1	4		T2	10651		T3	73446
all_pins[0]	values[0x1]	501745	1			T2	113		T3	700		T7	88
all_pins[0]	transitions[0x0=>0x1]	501736	1			T2	113		T3	700		T7	88
all_pins[0]	transitions[0x1=>0x0]	6192	1			T2	31		T3	113		T7	30
all_pins[1]	values[0x0]	98890483	1			T1	4		T2	10733		T3	74033
all_pins[1]	values[0x1]	6201	1			T2	31		T3	113		T7	30
all_pins[1]	transitions[0x0=>0x1]	5964	1			T2	31		T3	98		T34	1
all_pins[1]	transitions[0x1=>0x0]	284386	1			T3	8759		T7	8013		T14	342
all_pins[2]	values[0x0]	98612061	1			T1	4		T2	10764		T3	65372
all_pins[2]	values[0x1]	284623	1			T3	8774		T7	8043		T14	342
all_pins[2]	transitions[0x0=>0x1]	282922	1			T3	8711		T7	7986		T14	339
all_pins[2]	transitions[0x1=>0x0]	500076	1			T2	113		T3	637		T7	31