Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	679	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5596	1			T2	10		T3	39		T7	8
len_601_800	12589	1			T2	29		T3	110		T7	17
len_401_600	8370	1			T2	17		T3	69		T7	16
len_201_400	16517	1			T2	6		T3	32		T7	10
len_65_200	72805	1			T2	6		T3	86		T7	6
len_min_for_xof_require_squeeze	984	1			T2	1		T3	1		T35	1
len_keccak_block_sizes[72]	727	1			T3	1		T42	5		T112	2
len_keccak_block_sizes[104]	736	1			T32	1		T42	5		T117	9
len_keccak_block_sizes[136]	742	1			T3	3		T42	5		T112	2
len_keccak_block_sizes[144]	283	1			T3	1		T14	1		T42	5
len_keccak_block_sizes[168]	297	1			T32	1		T42	5		T185	5
len_datapath_width	13641	1			T3	21		T32	6		T34	3
len_2_63	210742	1			T2	3		T3	150		T7	28
len_1	56	1			T32	2		T112	1		T104	1