Summary for Variable in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for in_app_keymgr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
336956 |
1 |
|
|
T1 |
1 |
|
T2 |
72 |
|
T3 |
529 |
auto[1] |
3362 |
1 |
|
|
T3 |
22 |
|
T7 |
12 |
|
T8 |
5 |
Summary for Variable kmac_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
301850 |
1 |
|
|
T2 |
17 |
|
T3 |
163 |
|
T7 |
52 |
auto[1] |
38468 |
1 |
|
|
T1 |
1 |
|
T2 |
55 |
|
T3 |
388 |
Summary for Variable sideload
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sideload
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
326072 |
1 |
|
|
T1 |
1 |
|
T3 |
374 |
|
T7 |
87 |
auto[1] |
14246 |
1 |
|
|
T2 |
72 |
|
T3 |
177 |
|
T7 |
25 |
Summary for Cross sideload_cross
Samples crossed: sideload kmac_mode in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins for sideload_cross
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sw_kmac_valid_sideload |
14246 |
1 |
|
|
T2 |
72 |
|
T3 |
177 |
|
T7 |
25 |
sw_kmac_invalid_sideload |
326072 |
1 |
|
|
T1 |
1 |
|
T3 |
374 |
|
T7 |
87 |
app_valid_sideload |
14246 |
1 |
|
|
T2 |
72 |
|
T3 |
177 |
|
T7 |
25 |
app_invalid_sideload |
326072 |
1 |
|
|
T1 |
1 |
|
T3 |
374 |
|
T7 |
87 |