Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10743308 |
1 |
|
|
T2 |
12073 |
|
T3 |
52474 |
|
T7 |
9652 |
auto[1] |
10743299 |
1 |
|
|
T2 |
12073 |
|
T3 |
52474 |
|
T7 |
9652 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21250129 |
1 |
|
|
T2 |
24034 |
|
T3 |
104314 |
|
T7 |
19214 |
triple_byte_access |
78766 |
1 |
|
|
T2 |
32 |
|
T3 |
222 |
|
T7 |
30 |
halfword_access |
79344 |
1 |
|
|
T2 |
40 |
|
T3 |
226 |
|
T7 |
30 |
byte_access |
78368 |
1 |
|
|
T2 |
40 |
|
T3 |
186 |
|
T7 |
30 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10625069 |
1 |
|
|
T2 |
12017 |
|
T3 |
52157 |
|
T7 |
9607 |
auto[0] |
triple_byte_access |
39383 |
1 |
|
|
T2 |
16 |
|
T3 |
111 |
|
T7 |
15 |
auto[0] |
halfword_access |
39672 |
1 |
|
|
T2 |
20 |
|
T3 |
113 |
|
T7 |
15 |
auto[0] |
byte_access |
39184 |
1 |
|
|
T2 |
20 |
|
T3 |
93 |
|
T7 |
15 |
auto[1] |
word_access |
10625060 |
1 |
|
|
T2 |
12017 |
|
T3 |
52157 |
|
T7 |
9607 |
auto[1] |
triple_byte_access |
39383 |
1 |
|
|
T2 |
16 |
|
T3 |
111 |
|
T7 |
15 |
auto[1] |
halfword_access |
39672 |
1 |
|
|
T2 |
20 |
|
T3 |
113 |
|
T7 |
15 |
auto[1] |
byte_access |
39184 |
1 |
|
|
T2 |
20 |
|
T3 |
93 |
|
T7 |
15 |