Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100416898	1			T1	1391		T2	1469		T3	450052
all_values[1]	100416898	1			T1	1391		T2	1469		T3	450052
all_values[2]	100416898	1			T1	1391		T2	1469		T3	450052

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

519571

1

T1

379

T2

27

T7

186

auto[1]

300731123

1

T1

3794

T2

4380

T3

135015

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299731029

1

T1

4119

T2

3807

T3

134013

auto[1]

1519665

1

T1

54

T2

600

T3

10026

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	167735	1			T1	232		T2	17		T7	180
all_values[0]	auto[0]	auto[1]	2012	1			T1	6		T2	4		T7	6
all_values[0]	auto[1]	auto[0]	99742608	1			T1	1141		T2	1252		T3	446710
all_values[0]	auto[1]	auto[1]	504543	1			T1	12		T2	196		T3	3342
all_values[1]	auto[0]	auto[0]	156993	1			T2	4		T33	4		T34	1
all_values[1]	auto[0]	auto[1]	1419	1			T2	2		T33	2		T34	2
all_values[1]	auto[1]	auto[0]	99753350	1			T1	1373		T2	1265		T3	446710
all_values[1]	auto[1]	auto[1]	505136	1			T1	18		T2	198		T3	3342
all_values[2]	auto[0]	auto[0]	189862	1			T1	139		T4	1		T33	4
all_values[2]	auto[0]	auto[1]	1550	1			T1	2		T33	2		T34	2
all_values[2]	auto[1]	auto[0]	99720481	1			T1	1234		T2	1269		T3	446710
all_values[2]	auto[1]	auto[1]	505005	1			T1	16		T2	200		T3	3342