Unified Coverage Report :: Group :: kmac_env_pkg::config_masked_cg

Group : kmac_env_pkg::config_masked_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.88	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

---

Summary for Group kmac_env_pkg::config_masked_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	28	1	27	96.43
Crosses	4	0	4	100.00

Variables for Group kmac_env_pkg::config_masked_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
entropy_fast_process	2	0	2	100.00	100	1	1	2
entropy_mode	3	1	2	66.67	100	1	1	0
key_len	5	0	5	100.00	100	1	1	0
kmac_en	2	0	2	100.00	100	1	1	2
mode	3	0	3	100.00	100	1	1	0
msg_endian	2	0	2	100.00	100	1	1	2
sideload	2	0	2	100.00	100	1	1	2
state_endian	2	0	2	100.00	100	1	1	2
strength	5	0	5	100.00	100	1	1	0
xof_en	2	0	2	100.00	100	1	1	2

Crosses for Group kmac_env_pkg::config_masked_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
kmac_cross	1	0	1	100.00	100	1	1	0
cshake_cross	1	0	1	100.00	100	1	1	0
shake_cross	1	0	1	100.00	100	1	1	0
sha3_cross	1	0	1	100.00	100	1	1	0

Summary for Variable entropy_fast_process

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for entropy_fast_process

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

172138

1

T1

6

T2

70

T3

1165

auto[1]

171251

1

T1

8

T2

69

T3

1100

---

Summary for Variable entropy_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	1	2	66.67

Automatically Generated Bins for entropy_mode

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[EntropyModeNone]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[EntropyModeEdn]

172111

1

T2

139

T32

374

T34

2337

auto[EntropyModeSw]

171278

1

T1

14

T3

2265

T7

189

---

Summary for Variable key_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for key_len

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[Key128]	65606	1			T1	2		T2	27		T3	405
auto[Key192]	65354	1			T1	4		T2	32		T3	472
auto[Key256]	80840	1			T1	6		T2	26		T3	441
auto[Key384]	65883	1			T1	1		T2	24		T3	429
auto[Key512]	65706	1			T1	1		T2	30		T3	518

---

Summary for Variable kmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

309769

1

T1

8

T2

33

T3

2265

auto[1]

33620

1

T1

6

T2

106

T7

91

---

Summary for Variable mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[Sha3]	66601	1			T2	20		T32	374		T31	3
auto[Shake]	239700	1			T1	6		T2	13		T3	2265
auto[CShake]	37088	1			T1	8		T2	106		T7	119

---

Summary for Variable msg_endian

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msg_endian

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

171337

1

T1

5

T2

67

T3

1104

auto[1]

172052

1

T1

9

T2

72

T3

1161

---

Summary for Variable sideload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sideload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

332858

1

T1

11

T2

139

T3

2265

auto[1]

10531

1

T1

3

T7

34

T4

16

---

Summary for Variable state_endian

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for state_endian

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

171256

1

T1

9

T2

68

T3

1102

auto[1]

172133

1

T1

5

T2

71

T3

1163

---

Summary for Variable strength

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for strength

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[L128]	137540	1			T1	5		T2	65		T7	83
auto[L224]	19060	1			T2	5		T38	1		T154	5
auto[L256]	158265	1			T1	9		T2	59		T3	2265
auto[L384]	15889	1			T2	8		T31	2		T19	1
auto[L512]	12635	1			T2	2		T31	1		T160	246

---

Summary for Variable xof_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for xof_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

324093

1

T1

11

T2

64

T3

2265

auto[1]

19296

1

T1

3

T2

75

T7

24

---

Summary for Cross kmac_cross

Samples crossed: kmac_en xof_en strength key_len msg_endian state_endian entropy_mode entropy_fast_process

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	0	1	100.00

User Defined Cross Bins for kmac_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid_mode	0	Excluded
invalid_strength	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valid

33620

1

T1

6

T2

106

T7

91

---

Summary for Cross cshake_cross

Samples crossed: mode strength msg_endian state_endian entropy_mode entropy_fast_process

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	0	1	100.00

User Defined Cross Bins for cshake_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid_mode	0	Excluded
invalid_strength	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valid

37088

1

T1

8

T2

106

T7

119

---

Summary for Cross shake_cross

Samples crossed: mode strength msg_endian state_endian entropy_mode entropy_fast_process

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	0	1	100.00

User Defined Cross Bins for shake_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid_mode	0	Excluded
invalid_strength	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valid

239700

1

T1

6

T2

13

T3

2265

---

Summary for Cross sha3_cross

Samples crossed: mode strength msg_endian state_endian entropy_mode entropy_fast_process

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	0	1	100.00

User Defined Cross Bins for sha3_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid_mode	0	Excluded
invalid_strength	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valid

66601

1

T2

20

T32

374

T31

3