Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
345064 |
1 |
|
|
T1 |
28 |
|
T2 |
2 |
|
T3 |
4530 |
auto[1] |
344850 |
1 |
|
|
T2 |
276 |
|
T32 |
746 |
|
T34 |
4672 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
172560 |
1 |
|
|
T1 |
1 |
|
T2 |
82 |
|
T3 |
1134 |
lower_val |
170056 |
1 |
|
|
T1 |
10 |
|
T2 |
70 |
|
T3 |
1143 |
zero_val |
1776 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
3 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
258626 |
1 |
|
|
T1 |
12 |
|
T2 |
62 |
|
T3 |
2282 |
lower_val |
258754 |
1 |
|
|
T1 |
16 |
|
T2 |
70 |
|
T3 |
2248 |
zero_val |
172534 |
1 |
|
|
T2 |
146 |
|
T32 |
366 |
|
T34 |
2344 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
42924 |
1 |
|
|
T1 |
1 |
|
T3 |
571 |
|
T7 |
45 |
higher_val |
higher_val |
auto[1] |
21811 |
1 |
|
|
T2 |
18 |
|
T32 |
38 |
|
T34 |
320 |
higher_val |
lower_val |
auto[0] |
43223 |
1 |
|
|
T3 |
563 |
|
T7 |
55 |
|
T4 |
42 |
higher_val |
lower_val |
auto[1] |
21603 |
1 |
|
|
T2 |
20 |
|
T32 |
54 |
|
T34 |
299 |
higher_val |
zero_val |
auto[0] |
82 |
1 |
|
|
T32 |
1 |
|
T35 |
1 |
|
T203 |
1 |
higher_val |
zero_val |
auto[1] |
42917 |
1 |
|
|
T2 |
44 |
|
T32 |
92 |
|
T34 |
591 |
lower_val |
higher_val |
auto[0] |
42384 |
1 |
|
|
T1 |
6 |
|
T3 |
587 |
|
T7 |
48 |
lower_val |
higher_val |
auto[1] |
21422 |
1 |
|
|
T2 |
15 |
|
T32 |
57 |
|
T34 |
297 |
lower_val |
lower_val |
auto[0] |
42110 |
1 |
|
|
T1 |
4 |
|
T3 |
556 |
|
T7 |
50 |
lower_val |
lower_val |
auto[1] |
21310 |
1 |
|
|
T2 |
17 |
|
T32 |
56 |
|
T34 |
290 |
lower_val |
zero_val |
auto[0] |
80 |
1 |
|
|
T2 |
1 |
|
T49 |
1 |
|
T204 |
1 |
lower_val |
zero_val |
auto[1] |
42750 |
1 |
|
|
T2 |
37 |
|
T32 |
91 |
|
T34 |
580 |
zero_val |
higher_val |
auto[0] |
556 |
1 |
|
|
T1 |
1 |
|
T7 |
2 |
|
T4 |
1 |
zero_val |
higher_val |
auto[1] |
135 |
1 |
|
|
T18 |
3 |
|
T205 |
2 |
|
T14 |
2 |
zero_val |
lower_val |
auto[0] |
546 |
1 |
|
|
T3 |
3 |
|
T7 |
1 |
|
T33 |
1 |
zero_val |
lower_val |
auto[1] |
119 |
1 |
|
|
T34 |
1 |
|
T14 |
2 |
|
T206 |
1 |
zero_val |
zero_val |
auto[0] |
247 |
1 |
|
|
T2 |
1 |
|
T32 |
1 |
|
T35 |
1 |
zero_val |
zero_val |
auto[1] |
173 |
1 |
|
|
T34 |
1 |
|
T18 |
1 |
|
T69 |
2 |